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White Rabbit Switch - Gateware
Commit 169636bb authored by Adam Wujek's avatar Adam Wujek
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add generated files by python 

Signed-off-by: 's avatarAdam Wujek <dev_public@wujek.eu>
parent f11df4c5
Pipeline #5391 canceled with stages
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      .gitlab-ci.yml
      View file @ 169636bb
      ......@@ -48,11 +48,11 @@ job_scb_top_8p_syn:
      - du -sh *
      - cd top/bare_top
      - which python
      - python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_18p --ver "14.7"
      #- python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_18p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      - cd ../../modules/wrsw_hwiu
      - python2.7 gen_ver.py
      #- python2.7 gen_ver.py
      - cat gw_ver_pkg.vhd
      - cd ../../syn/scb_8ports
      - which hdlmake
      ......@@ -89,11 +89,11 @@ job_scb_top_18p_syn:
      - source ~/setup_ise147.sh
      - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
      - cd top/bare_top
      - python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_8p --ver "14.7"
      #- python2.7 gen_sdbsyn.py --user "CI ${GITLAB_USER_NAME}" --project WRS_8p --ver "14.7"
      - cat synthesis_descriptor.vhd
      - find / | grep hdlmake
      - cd ../../modules/wrsw_hwiu
      - python gen_ver.py
      #- python gen_ver.py
      - cat gw_ver_pkg.vhd
      - cd ../../syn/scb_18ports
      - which hdlmake
      ......
      modules/wrsw_hwiu/gw_ver_pkg.vhd 0 → 100644
      View file @ 169636bb
      library ieee;
      use ieee.std_logic_1164.all;
      --generated automatically by gen_ver.py script--
      package hwver_pkg is
      constant c_build_date : std_logic_vector(31 downto 0) := x"04051800";
      constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"0ed1937e";
      constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0434f154";
      constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"075bb7bb";
      end package;
      top/bare_top/synthesis_descriptor.vhd 0 → 100644
      View file @ 169636bb
      -- package generated automatically by gen_sdbsyn.py script --
      library ieee;
      use ieee.std_logic_1164.all;
      use work.wishbone_pkg.all;
      package synthesis_descriptor is
      constant c_sdb_repo_url : t_sdb_repo_url := (
      repo_url => "ssh://git@ohwr.org:7999/project/wr-switch-hdl.git ");
      constant c_sdb_top_syn_info : t_sdb_synthesis := (
      syn_module_name => "WRS_18p+ ",
      syn_commit_id => "28a57ea7 ",
      syn_tool_name => "ISE ",
      syn_tool_version => x"00000147",
      syn_date => x"20240506",
      syn_username => "CI Maciej Lipin");
      constant c_sdb_general_cores_syn_info : t_sdb_synthesis := (
      syn_module_name => "general-cores ",
      syn_commit_id => "434f1546 ",
      syn_tool_name => " ",
      syn_tool_version => x"00000000",
      syn_date => x"00000000",
      syn_username => " ");
      constant c_sdb_wr_cores_syn_info : t_sdb_synthesis := (
      syn_module_name => "wr-cores ",
      syn_commit_id => "75bb7bbf ",
      syn_tool_name => " ",
      syn_tool_version => x"00000000",
      syn_date => x"00000000",
      syn_username => " ");
      end package;
      \ No newline at end of file
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