Commit 16b2efe3 authored by Jesús Fernández's avatar Jesús Fernández

Fixed DMTD BUFR and BUFG locations in design

parent ec1cf5e8
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......@@ -26,7 +26,8 @@ NET "gm_clk_10mhz_n_i" LOC = K12;
#INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
#Not neccesary anymore
#INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
#INST "U_Buf_CLK_DMTD_DIV" LOC = BUFR_X1Y5;
INST "U_Buf_CLK_DMTD_DIV" LOC = BUFR_X1Y4;
INST "U_Buf_CLK_DMTD_62MHZ" LOC = BUFGCTRL_X0Y1;
#PIN "U_Buf_CLK_DMTD_DIV.O" CLOCK_DEDICATED_ROUTE=FALSE;
NET "gm_clk_62mhz_p_i" LOC = A10; #Former aux clk
......
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