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White Rabbit Switch - Gateware
Commit 22d782bf authored by Maciej Lipinski's avatar Maciej Lipinski
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[SYNTH] modifying 15-ports sythesis top for the new HW/design

parent f1e82d35
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Showing with 105 additions and 58 deletions
top/scb_15ports/scb_top_synthesis.ucf
View file @ 22d782bf
......@@ -13,6 +13,9 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
......@@ -96,7 +99,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
......@@ -137,18 +140,20 @@ NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3";
#NET "gtx_txn_o[1]" LOC="AN4";
#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[2]" LOC="AL4";
#NET "gtx_txp_o[2]" LOC="AM1";
#NET "gtx_txn_o[2]" LOC="AM2";
#NET "gtx_rxp_i[17]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[17]" LOC="AP6";
#NET "gtx_txp_o[17]" LOC="AP1";
#NET "gtx_txn_o[17]" LOC="AP2";
#NET "gtx_rxp_i[16]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[16]" LOC="AM6";
#NET "gtx_txp_o[16]" LOC="AN3";
#NET "gtx_txn_o[16]" LOC="AN4";
#NET "gtx_rxp_i[15]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[15]" LOC="AL4";
#NET "gtx_txp_o[15]" LOC="AM1";
#NET "gtx_txn_o[15]" LOC="AM2";
NET "gtx_rxp_i[14]" LOC="AJ3";
NET "gtx_rxn_i[14]" LOC="AJ4";
......@@ -258,13 +263,19 @@ NET "led_act_o[12]" LOC="AC29";
NET "led_act_o[13]" LOC="AC32";
NET "led_act_o[14]" LOC="AD31";
#NET "led_act_o[15]" LOC="AE32";
#NET "led_act_o[16]" LOC="AC28";
#NET "led_act_o[17]" LOC="AG33";
NET "mbl_scl_b[0]" LOC="AF31";
NET "mbl_sda_b[0]" LOC="AG32";
NET "mbl_scl_b[1]" LOC="AC25";
NET "mbl_sda_b[1]" LOC="AG31";
NET "clk_dmtd_divsel_o" LOC="AN15";
NET "mb_fan1_pwm_o" LOC="C12";
NET "mb_fan2_pwm_o" LOC="D12";
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
......@@ -340,9 +351,9 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
......@@ -613,7 +624,8 @@ INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wra
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.U_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/gen_network_stuff.U_RTU/U_Wrapped_RTU/U_WB_Slave/rtu_gcr_g_ena_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_en_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_rst_sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_set_sync0" TNM = Ignore_sync_ffs;
......@@ -639,37 +651,21 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/Mshreg_clk_i_d3" TNM = Ignore_DMTD;
TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
......
top/scb_15ports/scb_top_synthesis.vhd
View file @ 22d782bf
......@@ -99,6 +99,8 @@ entity scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
-- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
clk_dmtd_divsel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
......@@ -132,7 +134,13 @@ entity scb_top_synthesis is
led_act_o : out std_logic_vector(14 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0)
mbl_sda_b : inout std_logic_vector(1 downto 0);
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
);
......@@ -161,8 +169,11 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
-----------------------------------------------------------------------------
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "0.5ns";
attribute buffer_type : string;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......@@ -197,6 +208,13 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
attribute buffer_type of clk_dmtd : signal is "BUFG";
attribute buffer_type of clk_ref : signal is "BUFG";
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
......@@ -204,16 +222,22 @@ architecture Behavioral of scb_top_synthesis is
signal top_master_in, bridge_master_in : t_wishbone_master_in;
signal top_master_out, bridge_master_out : t_wishbone_master_out;
signal i2c_mbl_scl_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_scl_out : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_out : std_logic_vector(1 downto 0);
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
component scb_top_bare
generic (
g_num_ports : integer;
g_simulation : boolean;
g_without_network : boolean);
g_without_network : boolean;
g_with_TRU : boolean;
g_with_TATSU : boolean;
g_with_HWDU : boolean;
g_with_PSTATS : boolean);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -243,18 +267,22 @@ architecture Behavioral of scb_top_synthesis is
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11");
i2c_scl_oen_o : out std_logic_vector(2 downto 0);
i2c_scl_o : out std_logic_vector(2 downto 0);
i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111";
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
);
end component;
component chipscope_icon
......@@ -279,10 +307,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_mbl_scl_out(i) when i2c_mbl_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_mbl_sda_out(i) when i2c_mbl_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -535,7 +559,11 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => false)
g_without_network => false,
g_with_TRU => false,
g_with_TATSU => false,
g_with_HWDU => false,
g_with_PSTATS => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......@@ -565,17 +593,40 @@ begin
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
-- led_link_o => led_link_o,
led_act_o => led_act_o(c_NUM_PORTS-1 downto 0),
i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
i2c_mbl_scl_o => i2c_mbl_scl_out,
i2c_mbl_scl_i => mbl_scl_b,
i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
i2c_mbl_sda_o => i2c_mbl_sda_out,
i2c_mbl_sda_i => mbl_sda_b);
-- i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
-- i2c_mbl_scl_o => i2c_mbl_scl_out,
-- i2c_mbl_scl_i => mbl_scl_b,
-- i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
-- i2c_mbl_sda_o => i2c_mbl_sda_out,
-- i2c_mbl_sda_i => mbl_sda_b
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
i2c_scl_in(2) <= sensors_scl_b;
i2c_sda_in(2) <= sensors_sda_b;
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
sensors_scl_b <= i2c_scl_out(2) when i2c_scl_oen(2) = '0' else 'Z';
sensors_sda_b <= i2c_sda_out(2) when i2c_sda_oen(2) = '0' else 'Z';
end Behavioral;
......
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