Skip to content

W
White Rabbit Switch - Gateware
Commit 2aa61373 authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

swcore[new_mpm]: debugging, still leaking pages

parent e67ce727
Hide whitespace changes
Inline Side-by-side
Showing with 97 additions and 132 deletions
modules/wrsw_swcore/Manifest.py
View file @ 2aa61373
......@@ -15,9 +15,9 @@ files = [
"swc_multiport_page_allocator.vhd",
"swc_multiport_pck_pg_free_module.vhd",
"swc_ob_prio_queue.vhd",
"swc_packet_mem.vhd",
"swc_packet_mem_read_pump.vhd",
"swc_packet_mem_write_pump.vhd",
#"swc_packet_mem.vhd",
#"swc_packet_mem_read_pump.vhd",
#"swc_packet_mem_write_pump.vhd",
"swc_page_alloc.vhd",
"swc_page_alloc_old.vhd",
"swc_pck_pg_free_module.vhd",
......
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @ 2aa61373
......@@ -188,7 +188,7 @@ begin -- syn
zeros <= (others => '0');
-- this memory is read by the output of the MPM (called read pump)
PAGE_INDEX_LINKED_LIST_READ_PUMP : generic_dpram
PAGE_INDEX_LINKED_LIST_MPM : generic_dpram
generic map (
g_data_width => g_data_width,-- one bit for validating the data
g_size => g_page_num
......
modules/wrsw_swcore/swc_multiport_page_allocator.vhd
View file @ 2aa61373
......@@ -79,7 +79,7 @@ entity swc_multiport_page_allocator is
usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
free_last_pg_o : out std_logic_vector(g_num_ports - 1 downto 0);
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic
);
......@@ -154,8 +154,8 @@ architecture syn of swc_multiport_page_allocator is
signal free_done_feedback : std_logic_vector(g_num_ports-1 downto 0);
signal free_done : std_logic_vector(g_num_ports-1 downto 0);
signal free_last_pg : std_logic_vector(g_num_ports-1 downto 0);
signal free_last_pg_feedback : std_logic_vector(g_num_ports-1 downto 0);
signal free_last_usecnt : std_logic_vector(g_num_ports-1 downto 0);
signal free_last_usecnt_feedback : std_logic_vector(g_num_ports-1 downto 0);
signal force_free_done_feedback : std_logic_vector(g_num_ports-1 downto 0);
signal force_free_done : std_logic_vector(g_num_ports-1 downto 0);
......@@ -164,7 +164,7 @@ architecture syn of swc_multiport_page_allocator is
signal set_usecnt_done_feedback : std_logic_vector(g_num_ports-1 downto 0);
-- signal set_usecnt_done : std_logic_vector(g_num_ports-1 downto 0);
signal pg_free_last_pg : std_logic;
signal pg_free_last_usecnt : std_logic;
begin -- syn
......@@ -183,7 +183,7 @@ begin -- syn
rst_n_i => rst_n_i,
alloc_i => pg_alloc,
free_i => pg_free,
free_last_pg_o => pg_free_last_pg,
free_last_usecnt_o => pg_free_last_usecnt,
force_free_i => pg_force_free,
set_usecnt_i => pg_set_usecnt,
usecnt_i => pg_usecnt,
......@@ -264,7 +264,7 @@ begin -- syn
set_usecnt_done_feedback <= (others => '0');
force_free_done_feedback <= (others => '0');
free_last_pg <= (others => '0');
free_last_usecnt <= (others => '0');
else
-- recognizing on which port the allocation/deallocation/freeing process
......@@ -280,10 +280,10 @@ begin -- syn
if(request_grant(1 downto 0) = b"01") then
free_done_feedback(i) <= '1';
free_last_pg_feedback(i) <= pg_free_last_pg;
free_last_usecnt_feedback(i) <= pg_free_last_usecnt;
else
free_done_feedback(i) <= '0';
free_last_pg_feedback(i) <= '0';
free_last_usecnt_feedback(i) <= '0';
end if;
if(request_grant(1 downto 0) = b"10") then
......@@ -301,7 +301,7 @@ begin -- syn
else
alloc_done_feedback(i) <= '0';
free_done_feedback(i) <= '0';
free_last_pg_feedback(i) <= '0';
free_last_usecnt_feedback(i) <= '0';
set_usecnt_done_feedback(i) <= '0';
force_free_done_feedback(i) <= '0';
end if;
......@@ -309,7 +309,7 @@ begin -- syn
alloc_done <= alloc_done_feedback;
free_done <= free_done_feedback;
free_last_pg <= free_last_pg_feedback;
free_last_usecnt <= free_last_usecnt_feedback;
-- set_usecnt_done <= set_usecnt_done_feedback;
force_free_done <= force_free_done_feedback;
end if;
......@@ -318,7 +318,7 @@ begin -- syn
alloc_done_o <= alloc_done;
free_done_o <= free_done;
free_last_pg_o <= free_last_pg;
free_last_usecnt_o<= free_last_usecnt;
set_usecnt_done_o <= set_usecnt_done_feedback;--set_usecnt_done;
force_free_done_o <= force_free_done;
nomem_o <= pg_nomem;
......
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @ 2aa61373
......@@ -75,7 +75,7 @@ entity swc_multiport_pck_pg_free_module is
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_pg_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
......@@ -120,7 +120,7 @@ begin -- syn
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_last_pg_i => mmu_free_last_pg_i(i),
mmu_free_last_usecnt_i => mmu_free_last_usecnt_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_o => mmu_force_free_o(i),
......
modules/wrsw_swcore/swc_page_alloc.vhd
View file @ 2aa61373
......@@ -158,7 +158,7 @@ entity swc_page_allocator_new is
idle_o : out std_logic;
free_last_pg_o : out std_logic;
free_last_usecnt_o : out std_logic;
done_o : out std_logic; -- "early" done output (active HI).
-- Indicates that
......@@ -331,6 +331,6 @@ ram_ones <=(others => '1');
idle_o <= not (initializing or free_d0 or alloc_d0);
free_last_pg_o <= (not initializing) when (free_d0 = '1' and unsigned(usecnt_rddata) = 1) else '0';
free_last_usecnt_o <= (not initializing) when (free_d0 = '1' and unsigned(usecnt_rddata) = 1) else '0';
end syn;
modules/wrsw_swcore/swc_page_alloc_old.vhd
View file @ 2aa61373
......@@ -157,7 +157,7 @@ entity swc_page_allocator is
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
free_last_pg_o : out std_logic;
free_last_usecnt_o : out std_logic;
idle_o : out std_logic;
done_o : out std_logic; -- "early" done output (active HI).
......@@ -616,7 +616,7 @@ begin -- syn
nomem_o <= nomem;
free_last_pg_o <= '1' when (state = FREE_CHECK_USECNT and
free_last_usecnt_o <= '1' when (state = FREE_CHECK_USECNT and
usecnt_mem_rddata = std_logic_vector(to_unsigned(1, usecnt_mem_rddata'length ))) else
'0';
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ 2aa61373
......@@ -76,7 +76,7 @@ entity swc_pck_pg_free_module is
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_last_pg_i : in std_logic;
mmu_free_last_usecnt_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic;
......@@ -308,11 +308,14 @@ fsm_force_free : process(clk_i, rst_n_i)
if(mmu_free_done_i = '1') then
mmu_free <= '0';
-- TODO: if response from the MMU saying it's not the last to release, finish here
--if(next_page = ones ) then
if(eof = '1') then
if(eof = '1' or -- end of pck, all pages of this pck freed :)
mmu_free_last_usecnt_i = '0') then -- this means that still more readouts of the
-- pck is expected, so we just freed the first
-- page (therefore decremented the usecnt)
-- and that's all, we free all the pages of the
-- pck, only on the last usage
state <= S_IDLE;
else
current_page <= next_page;
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 2aa61373
......@@ -88,7 +88,7 @@ package swc_swcore_pkg is
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
free_last_pg_o : out std_logic;
free_last_usecnt_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
end component;
......@@ -111,7 +111,7 @@ package swc_swcore_pkg is
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
free_last_pg_o : out std_logic;
free_last_usecnt_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
end component;
......@@ -128,66 +128,7 @@ package swc_swcore_pkg is
grant_o : out std_logic_vector(g_num_ports_log2 - 1 downto 0);
grant_valid_o : out std_logic);
end component;
component swc_packet_mem_write_pump
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pump_data_width : integer ;--:= c_swc_pump_width
g_mem_addr_width : integer ;--:= c_swc_packet_mem_addr_width
g_page_addr_offset_width : integer ;--:= c_swc_page_offset_width
-- probably useless with new memory
g_packet_mem_multiply : integer --:= c_swc_packet_mem_multiply
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pgaddr_i : in std_logic_vector(g_page_addr_width-1 downto 0);
pgreq_i : in std_logic;
pgend_o : out std_logic;
pckstart_i : in std_logic;
drdy_i : in std_logic;
full_o : out std_logic;
flush_i : in std_logic;
ll_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_data_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
ll_wr_req_o : out std_logic;
ll_wr_done_i : in std_logic;
sync_i : in std_logic;
addr_o : out std_logic_vector(g_mem_addr_width -1 downto 0);
d_i : in std_logic_vector(g_pump_data_width -1 downto 0);
q_o : out std_logic_vector(g_pump_data_width * g_packet_mem_multiply - 1 downto 0);
we_o : out std_logic);
end component;
component swc_packet_mem_read_pump
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pump_data_width : integer ;--:= c_swc_pump_width
g_mem_addr_width : integer ;--:= c_swc_packet_mem_addr_width
g_page_addr_offset_width : integer ;--:= c_swc_page_offset_width
-- probably useless with new memory
g_packet_mem_multiply : integer --:= c_swc_packet_mem_multiply
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pgreq_i : in std_logic;
pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
pgend_o : out std_logic;
pckend_o : out std_logic;
drdy_o : out std_logic;
dreq_i : in std_logic;
sync_read_i : in std_logic;
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i: in std_logic;
sync_i : in std_logic;
d_o : out std_logic_vector(g_pump_data_width - 1 downto 0);
addr_o : out std_logic_vector(g_mem_addr_width - 1 downto 0);
q_i : in std_logic_vector(g_pump_data_width * g_packet_mem_multiply -1 downto 0));
end component;
component swc_multiport_linked_list is
generic (
g_num_ports : integer; --:= c_swc_num_ports
......@@ -378,7 +319,7 @@ package swc_swcore_pkg is
pgaddr_usecnt_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
free_last_pg_o : out std_logic_vector(g_num_ports - 1 downto 0);
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic
);
......@@ -550,7 +491,7 @@ component swc_multiport_pck_pg_free_module is
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_free_last_pg_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
......@@ -584,7 +525,7 @@ component swc_multiport_pck_pg_free_module is
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_free_last_pg_i : in std_logic;
mmu_free_last_usecnt_i : in std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 2aa61373
......@@ -266,7 +266,7 @@ architecture rtl of xswc_core is
-- MMU -> PPFM
signal mmu_force_free_done : std_logic_vector(g_num_ports-1 downto 0);
signal mmu_free_done : std_logic_vector(g_num_ports-1 downto 0);
signal mmu2ppfm_free_last_pg : std_logic_vector(g_num_ports-1 downto 0);
signal mmu2ppfm_free_last_usecnt : std_logic_vector(g_num_ports-1 downto 0);
---- end tmp
......@@ -456,7 +456,7 @@ architecture rtl of xswc_core is
mmu_free_o => ppfm_free,
mmu_free_done_i => mmu_free_done,
mmu_free_pgaddr_o => ppfm_free_pgaddr,
mmu_free_last_pg_i => mmu2ppfm_free_last_pg
mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt
);
......@@ -519,7 +519,7 @@ architecture rtl of xswc_core is
free_i => ppfm_free,
free_done_o => mmu_free_done,
pgaddr_free_i => ppfm_free_pgaddr,
free_last_pg_o => mmu2ppfm_free_last_pg,
free_last_usecnt_o => mmu2ppfm_free_last_usecnt,
force_free_i => ppfm_force_free,
force_free_done_o => mmu_force_free_done,
......
modules/wrsw_swcore/xswc_input_block.vhd
View file @ 2aa61373
......@@ -76,7 +76,7 @@
-- 2) make the dsel more generic
-- 3) test with mpm_dreq_i = LOW
-- 4) implement drop_on_SWCORE_stuck
--
-- 5) writing to the linked list / transfer -> we need to include waiting and stuff !!!
-------------------------------------------------------------------------------
......@@ -1027,14 +1027,22 @@ architecture syn of xswc_input_block is
ll_entry.size <= (others => '0');
--===================================================
else
if(mpm_dlast = '1') then
-- TODO:
if (in_pck_sof = '1') then
ll_wr_req <= '1';
ll_entry.valid <= '0';
ll_entry.eof <= '0';
ll_entry.addr <= pckstart_pageaddr;
ll_entry.dsel <= (others => '0');
ll_entry.size <= (others => '0');
ll_entry.next_page<= (others => '0');
elsif(mpm_dlast = '1') then
ll_wr_req <= '1';
ll_entry.valid <= '1';
ll_entry.eof <= '1';
ll_entry.addr <= mpm_pg_addr;
---------------- TODO: make it more generic !!!! ---------------------------------
if(snk_sel_d0 = "00") then
if(snk_sel_d0 = "10") then
ll_entry.dsel <= (others => '1');
else
ll_entry.dsel <= (others => '0');
......@@ -1062,7 +1070,6 @@ architecture syn of xswc_input_block is
-- assert false
-- report "Linked List done when not asked for";
end if;
end if;
end if;
end process ll_if;
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ 2aa61373
......@@ -176,6 +176,7 @@ architecture behavoural of xswc_output_block is
signal pck_start_pgaddr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
signal start_free_pck_addr : std_logic_vector(g_mpm_page_addr_width - 1 downto 0);
signal start_free_pck : std_logic;
signal ram_zeros : std_logic_vector(g_mpm_page_addr_width- 1 downto 0);
......@@ -506,11 +507,18 @@ begin -- behavoural
if rising_edge(clk_i) then
if(rst_n_i = '0') then
--========================================
s_send_pck <= S_IDLE;
src_out_int.stb <= '0';
src_out_int.we <= '1';
src_out_int.adr <= c_WRF_DATA;
src_out_int.cyc <= '0';
s_send_pck <= S_IDLE;
src_out_int.stb <= '0';
src_out_int.we <= '1';
src_out_int.adr <= c_WRF_DATA;
src_out_int.dat <= (others => '0');
src_out_int.cyc <= '0';
src_out_int.sel <= (others => '0');
start_free_pck <= '0';
start_free_pck_addr <= (others =>'0');
tmp_adr <= (others =>'0');
tmp_dat <= (others =>'0');
tmp_sel <= (others =>'0');
--========================================
else
-- default values
......@@ -520,8 +528,6 @@ begin -- behavoural
--===========================================================================================
when S_IDLE =>
--===========================================================================================
src_out_int.adr <= mpm2wb_adr_int;
src_out_int.dat <= mpm2wb_dat_int;
if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0') then
src_out_int.cyc <= '1';
......@@ -533,10 +539,13 @@ begin -- behavoural
when S_DATA =>
--===========================================================================================
if(src_i.stall = '0') then
src_out_int.adr <= mpm2wb_adr_int;
src_out_int.dat <= mpm2wb_dat_int;
if(mpm_dvalid_i = '1') then -- a avoid copying crap (i.e. XXX)
src_out_int.adr <= mpm2wb_adr_int;
src_out_int.dat <= mpm2wb_dat_int;
src_out_int.sel <= mpm2wb_sel_int;
end if;
src_out_int.stb <= mpm_dvalid_i;
src_out_int.sel <= mpm2wb_sel_int;
end if;
if(src_i.err = '1') then
......@@ -557,10 +566,11 @@ begin -- behavoural
if(mpm_dlast_i = '1')then
s_send_pck <= S_FINISH_CYCLE; -- we free page in EOF
end if;
tmp_adr <= mpm2wb_adr_int;
tmp_dat <= mpm2wb_dat_int;
tmp_sel <= mpm2wb_sel_int;
if(mpm_dvalid_i = '1') then -- a avoid copying crap (i.e. XXX)
tmp_adr <= mpm2wb_adr_int;
tmp_dat <= mpm2wb_dat_int;
tmp_sel <= mpm2wb_sel_int;
end if;
--===========================================================================================
when S_FLUSH_STALL =>
......@@ -573,7 +583,7 @@ begin -- behavoural
src_out_int.dat <= tmp_dat;
src_out_int.adr <= tmp_adr;
src_out_int.stb <= '1';
src_out_int.sel <= mpm2wb_sel_int;
src_out_int.sel <= tmp_sel;
s_send_pck <= S_DATA;
end if;
--===========================================================================================
......@@ -592,7 +602,8 @@ begin -- behavoural
when S_EOF =>
--===========================================================================================
if(ppfm_free = '0') then
start_free_pck <= '1';
start_free_pck <= '1';
start_free_pck_addr <= pck_start_pgaddr;
if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0') then
src_out_int.cyc <= '1';
......@@ -616,13 +627,13 @@ begin -- behavoural
when S_WAIT_FREE_PCK =>
--===========================================================================================
if(ppfm_free = '0') then
start_free_pck <= '1';
start_free_pck <= '1';
start_free_pck_addr <= pck_start_pgaddr;
if(s_prep_to_send = S_NEWPCK_PAGE_READY and src_i.err = '0') then
src_out_int.cyc <= '1';
s_send_pck <= S_DATA;
pck_start_pgaddr <= mpm_pg_addr;
src_out_int.adr <= mpm2wb_adr_int;
src_out_int.dat <= mpm2wb_dat_int;
src_out_int.cyc <= '1';
s_send_pck <= S_DATA;
pck_start_pgaddr <= mpm_pg_addr;
else
s_send_pck <= S_IDLE;
end if;
......@@ -657,12 +668,15 @@ begin -- behavoural
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
ppfm_free <= '0';
ppfm_free <= '0';
ppfm_free_pgaddr <= (others => '0');
else
if(start_free_pck = '1') then
ppfm_free <= '1';
ppfm_free <= '1';
ppfm_free_pgaddr <= start_free_pck_addr;
elsif(ppfm_free_done_i = '1') then
ppfm_free <='0';
ppfm_free <='0';
ppfm_free_pgaddr <= (others => '0');
end if;
end if;
end if;
......@@ -682,7 +696,7 @@ begin -- behavoural
'0';
mpm2wb_adr_int <= mpm_d_i(g_mpm_data_width -1 downto g_mpm_data_width - g_wb_addr_width);
mpm2wb_sel_int <= mpm_dsel_i & '1'; -- TODO: something generic
mpm2wb_sel_int <= '1' & mpm_dsel_i ; -- TODO: something generic
mpm2wb_dat_int <= mpm_d_i(g_wb_data_width -1 downto 0);
-- source out
......
testbench/swcore/swc_core_generic.sv
View file @ 2aa61373
......@@ -398,17 +398,17 @@ module main_generic;
@(posedge clk);
wait_cycles(500);
for(j=0;j<100;j++)
send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 1 /*mask*/);
// for(j=0;j<30;j++)
// send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 1 /*mask*/);
//for(j=0;j<`c_num_ports;j++) begin
/*
for(j=0;j<16;j++) begin
fork
automatic int p = j;
for(i=0; i<20; i++) begin
//mask = mask^(1<<(i%(`c_num_ports)));
mask =1<<p;
for(i=0; i<16; i++) begin
mask = mask^(1<<(i%(`c_num_ports)));
//mask =1<<p;
//send_random_packet(src,txed, 0 , 0,7 , mask);
//send_random_packet(src,txed, j, 0,7 , 16'hFFFF);
//$display("in fork %d",p);
......@@ -417,7 +417,7 @@ module main_generic;
join
//wait_cycles(500);
end
*/
wait_cycles(80000);
transferReport(); // here we wait for all pcks to be received and then make statistics
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment