swcore[new mpm]: bugfix in asynchronous MPM (the LL address mux-ed in…

swcore[new mpm]: bugfix in asynchronous MPM (the LL address mux-ed in p_ll_mux_addr was not synch-ed with delayed grand and data registering in mpm_rpath_io_block

swcore[new mpm]: bugfix in asynchronous MPM (the LL address mux-ed in…
swcore[new mpm]: bugfix in asynchronous MPM (the LL address mux-ed in p_ll_mux_addr was not synch-ed with delayed grand and data registering in mpm_rpath_io_block
e67ce727 · Maciej Lipinski · cb8a274f · e67ce727
Commit e67ce727 authored Feb 19, 2012 by Maciej Lipinski
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Showing with 12 additions and 2 deletions

mpm_read_path.vhd modules/wrsw_swcore/mpm/mpm_read_path.vhd +12 -2

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--- a/modules/wrsw_swcore/mpm/mpm_read_path.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_read_path.vhd
@@ -186,6 +186,8 @@ architecture rtl of mpm_read_path is

  signal fbm_data_reg : std_logic_vector(c_fbm_data_width-1 downto 0);

+  signal muxed : std_logic_vector(g_page_addr_width-1 downto 0);
+
 begin  -- rtl

 -- I/O structure serialization/deserialization
@@ -306,15 +308,23 @@ begin  -- rtl


  p_ll_mux_addr : process(clk_io_i)
-    variable muxed : std_logic_vector(g_page_addr_width-1 downto 0);
+    -- ML
+    --variable muxed : std_logic_vector(g_page_addr_width-1 downto 0);
+    -- ML
  begin
    if rising_edge(clk_io_i) then
      if rst_n_io_i = '0' then
        ll_addr_o <= (others => '0');
+        -- ML
+        muxed     <= (others => '0');
+        -- ML
      else
        for i in 0 to g_num_ports-1 loop
          if(io(i).ll_grant = '1') then
-            muxed := io(i).ll_addr;
+            -- ML
+            --muxed := io(i).ll_addr;
+            muxed <= io(i).ll_addr;
+            -- ML
          end if;
        end loop;  -- i
        ll_addr_o <= muxed;