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White Rabbit Switch - Gateware
Commit cb8a274f authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[new mpm]: freeing module adapted to new usecnt handling (the usecnt of… 

swcore[new mpm]: freeing module adapted to new usecnt handling (the usecnt of pck stored only with the first page). This is the first swcore version working fully with the new MPM, however, it is still buggy and needs tests
parent 885b5829
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Showing with 28 additions and 14 deletions
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @ cb8a274f
......@@ -52,7 +52,8 @@ entity swc_multiport_pck_pg_free_module is
generic(
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
);
port (
clk_i : in std_logic;
......@@ -67,15 +68,17 @@ entity swc_multiport_pck_pg_free_module is
ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
--ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_pg_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
......@@ -95,7 +98,8 @@ begin -- syn
LPD: swc_pck_pg_free_module
generic map(
g_page_addr_width => g_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_data_width => g_data_width
)
port map(
clk_i => clk_i,
......@@ -110,12 +114,13 @@ begin -- syn
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_data_i => ll_read_data_i,
ll_read_data_i => ll_read_data_i((i+1)*g_data_width - 1 downto i * g_data_width),
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_last_pg_i => mmu_free_last_pg_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_o => mmu_force_free_o(i),
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ cb8a274f
......@@ -54,7 +54,8 @@ use work.genram_pkg.all;
entity swc_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer --:= c_swc_freeing_fifo_size
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
);
port (
clk_i : in std_logic;
......@@ -69,12 +70,13 @@ entity swc_pck_pg_free_module is
ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(g_data_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_last_pg_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic;
......@@ -124,7 +126,7 @@ architecture syn of swc_pck_pg_free_module is
signal freeing_mode : std_logic_vector(1 downto 0);
signal fifo_clear_n : std_logic;
signal eof : std_logic;
begin -- syn
......@@ -216,6 +218,7 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_force_free <= '0';
mmu_free <= '0';
freeing_mode <= (others => '0');
eof <= '0';
--================================================
else
......@@ -227,6 +230,7 @@ fsm_force_free : process(clk_i, rst_n_i)
fifo_rd <= '0';
mmu_force_free <= '0';
mmu_free <= '0';
eof <= '0';
if(fifo_empty = '0') then
fifo_rd <= '1';
......@@ -251,8 +255,8 @@ fsm_force_free : process(clk_i, rst_n_i)
if(ll_read_valid_data_i = '1') then
ll_read_req <= '0';
next_page <= ll_read_data_i;
next_page <= ll_read_data_i(g_page_addr_width-1 downto 0);
eof <= ll_read_data_i(g_data_width -2 );
-- force free
if(freeing_mode = b"01") then
......@@ -272,6 +276,7 @@ fsm_force_free : process(clk_i, rst_n_i)
fifo_rd <= '0';
current_page <= (others => '0');
next_page <= (others => '0');
eof <= '0';
ll_read_req <= '0';
mmu_force_free <= '0';
freeing_mode <= (others => '0');
......@@ -286,7 +291,8 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_force_free <= '0';
if(next_page = ones ) then
--if(next_page = ones ) then
if(eof = '1') then
state <= S_IDLE;
else
current_page <= next_page;
......@@ -303,7 +309,10 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_free <= '0';
if(next_page = ones ) then
-- TODO: if response from the MMU saying it's not the last to release, finish here
--if(next_page = ones ) then
if(eof = '1') then
state <= S_IDLE;
else
current_page <= next_page;
......@@ -323,7 +332,7 @@ fsm_force_free : process(clk_i, rst_n_i)
ll_read_req <= '0';
mmu_force_free <= '0';
mmu_free <= '0';
eof <= '0';
end case;
end if;
......
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