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White Rabbit Switch - Gateware
Commit 4bb49626 authored by Maciej Lipinski's avatar Maciej Lipinski
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Merge branch 'v4-dev' into v4-dev-ff-dbg

parents 907ad8dc fb4c5e4b
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Showing with 19 additions and 8 deletions
testbench/scb_top/main.sv
View file @ 4bb49626
......@@ -1813,7 +1813,7 @@ module main;
/*
* testing forcing of full_match/fast_match -> for debugging
**/
/*
///*
initial begin
portUnderTest = 18'b010101010101010101;
g_enable_pck_gaps = 1;
......@@ -1825,15 +1825,15 @@ module main;
mac_single = 1;
// tx ,rx ,opt
rtu_dbg_f_fast_match = 1;
rtu_dbg_f_fast_match = 0;
rtu_dbg_f_full_match = 0;
end
*/
//*/
/** *************************** test scenario 58 ************************************* **/
/*
*
**/
///*
/*
initial begin
portUnderTest = 18'b111111111111111111;
g_enable_pck_gaps = 1;
......@@ -1889,9 +1889,10 @@ module main;
rtu_dbg_f_fast_match = 0;
rtu_dbg_f_full_match = 0;
tru_config_opt = 10;
g_tru_enable = 1;
end
*/
//////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////
......@@ -2611,6 +2612,14 @@ module main;
5 /*addition : simple mask reflecting on which port frame was rx-ed*/,
5 /*subtraction*/);
end
else if(tru_config_opt == 10) // test VID bug
begin
int i =0;
for(i=0;i<18;i++)
tru_drv.write_tru_tab( 1 /* valid */, i /* entry_addr */, 0 /* subentry_addr*/,
32'h00000000 /*pattern_mask*/, 32'h00000000 /* pattern_match*/,'h0 /* mode */,
32'hFFFFFFFF /*ports_mask */, 32'hFFFFFFFF /* ports_egress */, 32'hFFFFFFFF /* ports_ingress*/);
end
else // default config == 0
begin
tru_drv.write_tru_tab( 1 /* valid */, 0 /* entry_addr */, 0 /* subentry_addr*/,
......
top/bare_top/scb_top_bare.vhd
View file @ 4bb49626
......@@ -139,7 +139,7 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"05_08_13_01"; --DD_MM_YY_VV
constant c_GW_VERSION : std_logic_vector(31 downto 0) := x"09_08_13_00"; --DD_MM_YY_VV
constant c_NUM_WB_SLAVES : integer := 16;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
......@@ -148,7 +148,8 @@ architecture rtl of scb_top_bare is
constant c_DBG_V_SWCORE : integer := (3*10) + 2 + -- 3 resources, each has with of CNT of 10 bits +2 to make it 32
(g_num_ports+1)*16; -- states of input blocks (including NIC)
constant c_DBG_N_REGS : integer := 1 + integer(ceil(real(c_DBG_V_SWCORE)/real(32))); -- 32-bits debug registers which go to HWDU
constant c_ALL_EVENTS : integer := c_RTU_EVENTS + c_epevents_sz;
constant c_TRU_EVENTS : integer := 1;
constant c_ALL_EVENTS : integer := c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
constant c_DUMMY_RMON : boolean := false; -- define TRUE to enable dummy_rmon module for debugging PSTAT
-- constant c_epevents_sz : integer := 15;
-------------------------------------------------------------------------------
......@@ -959,6 +960,7 @@ begin
gen_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
rmon_events((i+1)*c_ALL_EVENTS-1 downto i*c_ALL_EVENTS) <=
std_logic(tru_resp.respMask(i) and tru_resp.valid) &
rtu_events((i+1)*c_RTU_EVENTS-1 downto i*c_RTU_EVENTS) &
ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
end generate gen_events_assemble;
......
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