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White Rabbit Switch - Gateware
Commits
54334638
Commit
54334638
authored
Jul 01, 2019
by
li hongming
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Plain Diff
add NET TIG constraints in ucf for easy compilation.
parent
db3fb858
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6 changed files
with
589 additions
and
561 deletions
+589
-561
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+3
-3
test_scb.xise
syn/scb_18ports/test_scb.xise
+16
-16
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+4
-2
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+2
-1
scb_top_synthesis.ucf
top/scb_18ports/scb_top_synthesis.ucf
+541
-515
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+23
-24
No files found.
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
54334638
...
@@ -58,7 +58,7 @@ entity wrsw_rt_subsystem is
...
@@ -58,7 +58,7 @@ entity wrsw_rt_subsystem is
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
--
clk_500_o : out std_logic;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
;
rst_n_o
:
out
std_logic
;
...
@@ -209,7 +209,7 @@ architecture rtl of wrsw_rt_subsystem is
...
@@ -209,7 +209,7 @@ architecture rtl of wrsw_rt_subsystem is
pps_valid_i
:
in
std_logic
;
pps_valid_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
--
clk_500_o : out std_logic;
ppsdel_tap_i
:
in
std_logic_vector
(
4
downto
0
);
ppsdel_tap_i
:
in
std_logic_vector
(
4
downto
0
);
ppsdel_tap_o
:
out
std_logic_vector
(
4
downto
0
);
ppsdel_tap_o
:
out
std_logic_vector
(
4
downto
0
);
ppsdel_tap_wr_o
:
out
std_logic
;
ppsdel_tap_wr_o
:
out
std_logic
;
...
@@ -485,7 +485,7 @@ begin -- rtl
...
@@ -485,7 +485,7 @@ begin -- rtl
pps_valid_i
=>
pps_valid
,
pps_valid_i
=>
pps_valid
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_500_o
=>
clk_500_o
,
--
clk_500_o => clk_500_o,
ppsdel_tap_i
=>
ppsdel_tap_i
,
ppsdel_tap_i
=>
ppsdel_tap_i
,
ppsdel_tap_o
=>
ppsdel_tap_o
,
ppsdel_tap_o
=>
ppsdel_tap_o
,
ppsdel_tap_wr_o
=>
ppsdel_tap_wr_o
,
ppsdel_tap_wr_o
=>
ppsdel_tap_wr_o
,
...
...
syn/scb_18ports/test_scb.xise
View file @
54334638
...
@@ -97,8 +97,8 @@
...
@@ -97,8 +97,8 @@
<property
xil_pn:name=
"Enable Hardware Co-Simulation"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Hardware Co-Simulation"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Internal Done Pipe"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Internal Done Pipe"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Threading"
xil_pn:value=
"
2"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Enable Multi-Threading"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Enable Multi-Threading par virtex5"
xil_pn:value=
"
4"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Enable Multi-Threading par virtex5"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Enable Outputs (Output Events)"
xil_pn:value=
"Default (5)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Outputs (Output Events)"
xil_pn:value=
"Default (5)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream virtex6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream virtex6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
@@ -109,8 +109,8 @@
...
@@ -109,8 +109,8 @@
<property
xil_pn:name=
"Evaluation Development Board"
xil_pn:value=
"None Specified"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Evaluation Development Board"
xil_pn:value=
"None Specified"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of Deprecated EDK Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of Deprecated EDK Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of EDK Sub-Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Exclude Compilation of EDK Sub-Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map virtex6"
xil_pn:value=
"
1"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Extra Cost Tables Map virtex6"
xil_pn:value=
"
0"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Extra Effort (Highest PAR level only)"
xil_pn:value=
"
Normal
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Extra Effort (Highest PAR level only)"
xil_pn:value=
"
Continue on Impossible
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"FPGA Start-Up Clock"
xil_pn:value=
"CCLK"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FPGA Start-Up Clock"
xil_pn:value=
"CCLK"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Encoding Algorithm"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Encoding Algorithm"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
...
@@ -126,7 +126,7 @@
...
@@ -126,7 +126,7 @@
<property
xil_pn:name=
"Generate Constraints Interaction Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Constraints Interaction Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Constraints Interaction Report Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Constraints Interaction Report Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Datasheet Section"
xil_pn:value=
"false"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Generate Datasheet Section"
xil_pn:value=
"false"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Generate Datasheet Section Post Trace"
xil_pn:value=
"
true"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Generate Datasheet Section Post Trace"
xil_pn:value=
"
false"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Generate Detailed MAP Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Detailed MAP Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Multiple Hierarchical Netlist Files"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Multiple Hierarchical Netlist Files"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Power Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Power Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
@@ -161,7 +161,7 @@
...
@@ -161,7 +161,7 @@
<property
xil_pn:name=
"JTAG Pin TDO"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDO"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TMS"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TMS"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG to System Monitor Connection"
xil_pn:value=
"Enable"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG to System Monitor Connection"
xil_pn:value=
"Enable"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Keep Hierarchy"
xil_pn:value=
"
No"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Keep Hierarchy"
xil_pn:value=
"
Soft"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"LUT Combining Map"
xil_pn:value=
"Auto"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"LUT Combining Map"
xil_pn:value=
"Auto"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"LUT Combining Xst"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"LUT Combining Xst"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Language"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Language"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
...
@@ -172,7 +172,7 @@
...
@@ -172,7 +172,7 @@
<property
xil_pn:name=
"Library for Verilog Sources"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Library for Verilog Sources"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Load glbl"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Load glbl"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Manual Implementation Compile Order"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Manual Implementation Compile Order"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Map Slice Logic into Unused Block RAMs"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Map Slice Logic into Unused Block RAMs"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Max Fanout"
xil_pn:value=
"100000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Max Fanout"
xil_pn:value=
"100000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Compression"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Compression"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Number of Lines in Report"
xil_pn:value=
"1000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Number of Lines in Report"
xil_pn:value=
"1000"
xil_pn:valueState=
"default"
/>
...
@@ -182,10 +182,10 @@
...
@@ -182,10 +182,10 @@
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"As Optimized"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"As Optimized"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Translation Type"
xil_pn:value=
"Timestamp"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Translation Type"
xil_pn:value=
"Timestamp"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"32"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"32"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report"
xil_pn:value=
"
3"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report"
xil_pn:value=
"
10"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report Post Trace"
xil_pn:value=
"
3"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report Post Trace"
xil_pn:value=
"
10"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Optimization Effort virtex6"
xil_pn:value=
"High"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Optimization Effort virtex6"
xil_pn:value=
"High"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"
Area"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"
Speed"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"true"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"true"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
@@ -207,7 +207,7 @@
...
@@ -207,7 +207,7 @@
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"scb_top_synthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"scb_top_synthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"For
Inputs and Outputs
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"For
Outputs Only
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"ff1156"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"ff1156"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
@@ -215,7 +215,7 @@
...
@@ -215,7 +215,7 @@
<property
xil_pn:name=
"Place & Route Effort Level (Overall)"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place & Route Effort Level (Overall)"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Reentrant Route"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Reentrant Route"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Placer Effort Level Map"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Effort Level Map"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"
Normal
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"
Continue on Impossible
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Port to be used"
xil_pn:value=
"Auto - default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Port to be used"
xil_pn:value=
"Auto - default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Map Simulation Model Name"
xil_pn:value=
"scb_top_synthesis_map.vhd"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Map Simulation Model Name"
xil_pn:value=
"scb_top_synthesis_map.vhd"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Place & Route Simulation Model Name"
xil_pn:value=
"scb_top_synthesis_timesim.vhd"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Place & Route Simulation Model Name"
xil_pn:value=
"scb_top_synthesis_timesim.vhd"
xil_pn:valueState=
"default"
/>
...
@@ -246,12 +246,12 @@
...
@@ -246,12 +246,12 @@
<property
xil_pn:name=
"Rename Top Level Architecture To"
xil_pn:value=
"Structure"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Architecture To"
xil_pn:value=
"Structure"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Entity to"
xil_pn:value=
"scb_top_synthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Entity to"
xil_pn:value=
"scb_top_synthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Module To"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Module To"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint"
xil_pn:value=
"
true"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint"
xil_pn:value=
"
false"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint Post Trace"
xil_pn:value=
"
true"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint Post Trace"
xil_pn:value=
"
false"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Type"
xil_pn:value=
"
Verbose Report"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Report Type"
xil_pn:value=
"
Error Report"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Report Type Post Trace"
xil_pn:value=
"
Verbose Report"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Report Type Post Trace"
xil_pn:value=
"
Error Report"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths Post Trace"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths Post Trace"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
...
...
top/bare_top/scb_top_bare.vhd
View file @
54334638
...
@@ -91,7 +91,7 @@ entity scb_top_bare is
...
@@ -91,7 +91,7 @@ entity scb_top_bare is
clk_aux_p_o
:
out
std_logic
;
-- going to CLK2 SMC on the front pannel, by
clk_aux_p_o
:
out
std_logic
;
-- going to CLK2 SMC on the front pannel, by
clk_aux_n_o
:
out
std_logic
;
-- default it's 10MHz, but is configurable
clk_aux_n_o
:
out
std_logic
;
-- default it's 10MHz, but is configurable
clk_500_o
:
out
std_logic
;
--
clk_500_o : out std_logic;
-- Muxed system clock
-- Muxed system clock
clk_sys_o
:
out
std_logic
;
clk_sys_o
:
out
std_logic
;
...
@@ -166,6 +166,7 @@ entity scb_top_bare is
...
@@ -166,6 +166,7 @@ entity scb_top_bare is
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
link_los_i
:
in
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
...
@@ -531,7 +532,7 @@ begin
...
@@ -531,7 +532,7 @@ begin
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_500_o
=>
clk_500_o
,
--
clk_500_o => clk_500_o,
rst_n_i
=>
rst_n_sys
,
rst_n_i
=>
rst_n_sys
,
rst_n_o
=>
rst_n_periph
,
rst_n_o
=>
rst_n_periph
,
wb_i
=>
cnx_master_out
(
c_SLAVE_RT_SUBSYSTEM
),
wb_i
=>
cnx_master_out
(
c_SLAVE_RT_SUBSYSTEM
),
...
@@ -696,6 +697,7 @@ begin
...
@@ -696,6 +697,7 @@ begin
phy_rst_o
=>
phys_o
(
i
)
.
rst
,
phy_rst_o
=>
phys_o
(
i
)
.
rst
,
phy_loopen_o
=>
phys_o
(
i
)
.
loopen
,
phy_loopen_o
=>
phys_o
(
i
)
.
loopen
,
phy_sfp_los_i
=>
link_los_i
(
i
),
phy_enable_o
=>
phys_o
(
i
)
.
enable
,
phy_enable_o
=>
phys_o
(
i
)
.
enable
,
phy_rdy_i
=>
phys_i
(
i
)
.
rdy
,
phy_rdy_i
=>
phys_i
(
i
)
.
rdy
,
phy_ref_clk_i
=>
phys_i
(
i
)
.
ref_clk
,
phy_ref_clk_i
=>
phys_i
(
i
)
.
ref_clk
,
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
54334638
...
@@ -216,7 +216,7 @@ package wrsw_top_pkg is
...
@@ -216,7 +216,7 @@ package wrsw_top_pkg is
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
--
clk_500_o : out std_logic;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
;
rst_n_o
:
out
std_logic
;
wb_i
:
in
t_wishbone_slave_in
;
wb_i
:
in
t_wishbone_slave_in
;
...
@@ -326,6 +326,7 @@ package wrsw_top_pkg is
...
@@ -326,6 +326,7 @@ package wrsw_top_pkg is
clk_sel_o
:
out
std_logic
;
clk_sel_o
:
out
std_logic
;
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
link_los_i
:
in
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
gpio_o
:
out
std_logic_vector
(
31
downto
0
);
gpio_o
:
out
std_logic_vector
(
31
downto
0
);
...
...
top/scb_18ports/scb_top_synthesis.ucf
View file @
54334638
This source diff could not be displayed because it is too large. You can
view the blob
instead.
top/scb_18ports/scb_top_synthesis.vhd
View file @
54334638
...
@@ -77,8 +77,6 @@ entity scb_top_synthesis is
...
@@ -77,8 +77,6 @@ entity scb_top_synthesis is
-- 10MHz out clock generated from oserdes
-- 10MHz out clock generated from oserdes
clk_aux_p_o
:
out
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
-- clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Atmel EBI bus
-- Atmel EBI bus
...
@@ -191,6 +189,7 @@ entity scb_top_synthesis is
...
@@ -191,6 +189,7 @@ entity scb_top_synthesis is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
led_act_o
:
out
std_logic_vector
(
17
downto
0
);
led_act_o
:
out
std_logic_vector
(
17
downto
0
);
link_los_i
:
in
std_logic_vector
(
17
downto
0
);
mbl_scl_b
:
inout
std_logic_vector
(
1
downto
0
);
mbl_scl_b
:
inout
std_logic_vector
(
1
downto
0
);
mbl_sda_b
:
inout
std_logic_vector
(
1
downto
0
);
mbl_sda_b
:
inout
std_logic_vector
(
1
downto
0
);
...
@@ -343,7 +342,6 @@ architecture Behavioral of scb_top_synthesis is
...
@@ -343,7 +342,6 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_mul_locked_i
:
in
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_p_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_aux_n_o
:
out
std_logic
;
clk_500_o
:
out
std_logic
;
clk_sys_o
:
out
std_logic
;
clk_sys_o
:
out
std_logic
;
cpu_wb_i
:
in
t_wishbone_slave_in
;
cpu_wb_i
:
in
t_wishbone_slave_in
;
cpu_wb_o
:
out
t_wishbone_slave_out
;
cpu_wb_o
:
out
t_wishbone_slave_out
;
...
@@ -357,7 +355,6 @@ architecture Behavioral of scb_top_synthesis is
...
@@ -357,7 +355,6 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o
:
out
std_logic
;
dac_main_sync_n_o
:
out
std_logic
;
dac_main_sclk_o
:
out
std_logic
;
dac_main_sclk_o
:
out
std_logic
;
dac_main_data_o
:
out
std_logic
;
dac_main_data_o
:
out
std_logic
;
-- pll_status_i : in std_logic;
pll_mosi_o
:
out
std_logic
;
pll_mosi_o
:
out
std_logic
;
pll_miso_i
:
in
std_logic
;
pll_miso_i
:
in
std_logic
;
pll_sck_o
:
out
std_logic
;
pll_sck_o
:
out
std_logic
;
...
@@ -378,19 +375,20 @@ architecture Behavioral of scb_top_synthesis is
...
@@ -378,19 +375,20 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_divsel_o
:
out
std_logic
;
clk_dmtd_divsel_o
:
out
std_logic
;
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
link_los_i
:
in
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_link_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
led_act_o
:
out
std_logic_vector
(
g_num_ports
-1
downto
0
);
gpio_o
:
out
std_logic_vector
(
31
downto
0
);
gpio_o
:
out
std_logic_vector
(
31
downto
0
);
gpio_i
:
in
std_logic_vector
(
31
downto
0
);
gpio_i
:
in
std_logic_vector
(
31
downto
0
);
i2c_scl_oen_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_scl_oen_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_scl_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_scl_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_scl_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
i2c_scl_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
i2c_sda_oen_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_sda_oen_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_sda_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_sda_o
:
out
std_logic_vector
(
2
downto
0
);
i2c_sda_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
i2c_sda_i
:
in
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
mb_fan1_pwm_o
:
out
std_logic
;
mb_fan1_pwm_o
:
out
std_logic
;
mb_fan2_pwm_o
:
out
std_logic
;
mb_fan2_pwm_o
:
out
std_logic
;
spll_dbg_o
:
out
std_logic_vector
(
5
downto
0
)
spll_dbg_o
:
out
std_logic_vector
(
5
downto
0
)
);
);
end
component
;
end
component
;
...
@@ -561,7 +559,7 @@ begin
...
@@ -561,7 +559,7 @@ begin
gen_with_ext_AD9516
:
if
(
g_with_ext_AD9516
)
generate
gen_with_ext_AD9516
:
if
(
g_with_ext_AD9516
)
generate
U_Buf_ext_clk_62mhz
:
IBUF
G
DS
U_Buf_ext_clk_62mhz
:
IBUFDS
generic
map
(
generic
map
(
DIFF_TERM
=>
true
,
DIFF_TERM
=>
true
,
IOSTANDARD
=>
"LVDS_25"
)
IOSTANDARD
=>
"LVDS_25"
)
...
@@ -578,7 +576,7 @@ begin
...
@@ -578,7 +576,7 @@ begin
O
=>
ext_clk_62mhz_bufr
);
O
=>
ext_clk_62mhz_bufr
);
clk_ext_mul
<=
ext_clk_62mhz_bufr
;
clk_ext_mul
<=
ext_clk_62mhz_bufr
;
clk_ext_mul_locked
<=
ext_pll_lock_i
;
-- Fixme, connect to ext_pll_status
clk_ext_mul_locked
<=
ext_pll_lock_i
;
end
generate
gen_with_ext_AD9516
;
end
generate
gen_with_ext_AD9516
;
...
@@ -770,7 +768,6 @@ begin
...
@@ -770,7 +768,6 @@ begin
clk_ext_mul_locked_i
=>
clk_ext_mul_locked
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_p_o
=>
clk_aux_p_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_aux_n_o
=>
clk_aux_n_o
,
clk_500_o
=>
clk_500_o
,
cpu_wb_i
=>
top_master_out
,
cpu_wb_i
=>
top_master_out
,
cpu_wb_o
=>
top_master_in
,
cpu_wb_o
=>
top_master_in
,
cpu_irq_n_o
=>
cpu_irq_n_o
,
cpu_irq_n_o
=>
cpu_irq_n_o
,
...
@@ -804,17 +801,19 @@ begin
...
@@ -804,17 +801,19 @@ begin
gpio_i
=>
x"00000000"
,
gpio_i
=>
x"00000000"
,
phys_o
=>
to_phys
(
c_NUM_PORTS
-1
downto
0
),
phys_o
=>
to_phys
(
c_NUM_PORTS
-1
downto
0
),
phys_i
=>
from_phys
(
c_NUM_PORTS
-1
downto
0
),
phys_i
=>
from_phys
(
c_NUM_PORTS
-1
downto
0
),
-- led_link_o => led_link_o,
link_los_i
=>
link_los_i
(
c_NUM_PORTS
-1
downto
0
),
-- led_link_o => led_link_o,
led_act_o
=>
led_act_o
(
c_NUM_PORTS
-1
downto
0
),
led_act_o
=>
led_act_o
(
c_NUM_PORTS
-1
downto
0
),
i2c_scl_oen_o
=>
i2c_scl_oen
,
i2c_scl_oen_o
=>
i2c_scl_oen
,
i2c_scl_o
=>
i2c_scl_out
,
i2c_scl_o
=>
i2c_scl_out
,
i2c_scl_i
=>
i2c_scl_in
,
i2c_scl_i
=>
i2c_scl_in
,
i2c_sda_oen_o
=>
i2c_sda_oen
,
i2c_sda_oen_o
=>
i2c_sda_oen
,
i2c_sda_o
=>
i2c_sda_out
,
i2c_sda_o
=>
i2c_sda_out
,
i2c_sda_i
=>
i2c_sda_in
,
i2c_sda_i
=>
i2c_sda_in
,
-- mb_fan1_pwm_o => mb_fan1_pwm_o,
-- mb_fan1_pwm_o => mb_fan1_pwm_o,
-- mb_fan2_pwm_o => mb_fan2_pwm_o,
-- mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o
=>
open
);
spll_dbg_o
=>
open
);
i2c_scl_in
(
1
downto
0
)
<=
mbl_scl_b
(
1
downto
0
);
i2c_scl_in
(
1
downto
0
)
<=
mbl_scl_b
(
1
downto
0
);
i2c_sda_in
(
1
downto
0
)
<=
mbl_sda_b
(
1
downto
0
);
i2c_sda_in
(
1
downto
0
)
<=
mbl_sda_b
(
1
downto
0
);
...
...
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