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Commit 6cffb99a authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-azing]: no more global constants !!! -> fully generic-azed,… 

swcore[generic-azing]: no more global constants !!! -> fully generic-azed, removed global constants from the swc_swcore_pkg.vhd (not tested yet for different generic values, there is a known problem inherited from global consants - does not work when some configs are changed
parent 9797d04d
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Showing with 468 additions and 536 deletions
modules/wrsw_swcore/Manifest.py
View file @ 6cffb99a
......@@ -11,13 +11,13 @@ files = [
"swc_swcore_pkg.vhd",
"swc_block_alloc.vhd",
"swc_core.vhd",
"swc_input_block.vhd",
#"swc_input_block.vhd",
#"swc_lost_pck_dealloc.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
"swc_multiport_pck_pg_free_module.vhd",
"swc_ob_prio_queue.vhd",
"swc_output_block.vhd",
#"swc_output_block.vhd",
"swc_packet_mem.vhd",
"swc_packet_mem_read_pump.vhd",
"swc_packet_mem_write_pump.vhd",
......
modules/wrsw_swcore/swc_core.vhd
View file @ 6cffb99a
......@@ -57,7 +57,7 @@ entity swc_core is
g_mem_size : integer ;--:= c_swc_packet_mem_size
g_page_size : integer ;--:= c_swc_page_size
g_prio_num : integer ;--:= c_swc_output_prio_num;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
......@@ -105,6 +105,7 @@ architecture rtl of swc_core is
constant c_page_num : integer := (g_mem_size / g_page_size); -- 65536/64 = 1024 -- c_swc_packet_mem_num_pages
constant c_page_addr_width : integer := integer(CEIL(LOG2(real(c_page_num-1)))); --c_swc_page_addr_width
constant c_max_pck_size_width : integer := integer(CEIL(LOG2(real(g_max_pck_size-1)))); -- c_swc_max_pck_size_width
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Memory Management Unit<<
----------------------------------------------------------------------------------------------------
......@@ -145,7 +146,7 @@ architecture rtl of swc_core is
signal ib_pageaddr_to_pta : std_logic_vector(g_num_ports * c_page_addr_width - 1 downto 0);
signal ib_mask : std_logic_vector(g_num_ports * g_num_ports - 1 downto 0);
signal ib_prio : std_logic_vector(g_num_ports * c_prio_width - 1 downto 0);
signal ib_pck_size : std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
signal ib_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
-- Pck Transfer Arbiter -> Input Block
signal pta_transfer_ack : std_logic_vector(g_num_ports - 1 downto 0);
......@@ -158,7 +159,7 @@ architecture rtl of swc_core is
signal pta_data_valid : std_logic_vector(g_num_ports -1 downto 0);
signal pta_pageaddr : std_logic_vector(g_num_ports * c_page_addr_width - 1 downto 0);
signal pta_prio : std_logic_vector(g_num_ports * c_prio_width - 1 downto 0);
signal pta_pck_size : std_logic_vector(g_num_ports * g_max_pck_size_width - 1 downto 0);
signal pta_pck_size : std_logic_vector(g_num_ports * c_max_pck_size_width - 1 downto 0);
-- Input Block -> Pck Transfer Arbiter
signal ob_ack : std_logic_vector(g_num_ports -1 downto 0);
......@@ -258,7 +259,7 @@ architecture rtl of swc_core is
g_page_addr_width => c_page_addr_width,
g_num_ports => g_num_ports,
g_prio_width => c_prio_width,
g_max_pck_size_width => g_max_pck_size_width,
g_max_pck_size_width => c_max_pck_size_width,
g_usecount_width => c_usecount_width,
g_data_width => g_data_width,
g_ctrl_width => g_ctrl_width,
......@@ -327,7 +328,7 @@ architecture rtl of swc_core is
pta_pageaddr_o => ib_pageaddr_to_pta((i + 1) * c_page_addr_width -1 downto i * c_page_addr_width),
pta_mask_o => ib_mask ((i + 1) * g_num_ports -1 downto i * g_num_ports),
pta_prio_o => ib_prio ((i + 1) * c_prio_width -1 downto i * c_prio_width),
pta_pck_size_o => ib_pck_size ((i + 1) * g_max_pck_size_width -1 downto i * g_max_pck_size_width)
pta_pck_size_o => ib_pck_size ((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width)
);
......@@ -336,7 +337,7 @@ architecture rtl of swc_core is
OUTPUT_BLOCK: xswc_output_block
generic map(
g_page_addr_width => c_page_addr_width,
g_max_pck_size_width => g_max_pck_size_width,
g_max_pck_size_width => c_max_pck_size_width,
g_data_width => g_data_width,
g_ctrl_width => g_ctrl_width,
g_output_block_per_prio_fifo_size => g_output_block_per_prio_fifo_size,
......@@ -352,7 +353,7 @@ architecture rtl of swc_core is
pta_transfer_data_valid_i=> pta_data_valid(i),
pta_pageaddr_i => pta_pageaddr((i + 1) * c_page_addr_width -1 downto i * c_page_addr_width),
pta_prio_i => pta_prio ((i + 1) * c_prio_width -1 downto i * c_prio_width),
pta_pck_size_i => pta_pck_size((i + 1) * g_max_pck_size_width -1 downto i * g_max_pck_size_width),
pta_pck_size_i => pta_pck_size((i + 1) * c_max_pck_size_width -1 downto i * c_max_pck_size_width),
pta_transfer_data_ack_o => ob_ack(i),
-------------------------------------------------------------------------------
-- I/F with Multiport Memory (MPM)
......@@ -491,6 +492,16 @@ architecture rtl of swc_core is
-- MultiPort Memory (MPM) [ 1 module]
----------------------------------------------------------------------
MUPTIPORT_MEMORY: swc_packet_mem
generic map(
g_mem_size => g_mem_size,
g_num_ports => g_num_ports,
g_page_num => c_page_num,
g_page_addr_width => c_page_addr_width,
g_data_width => g_data_width,
g_ctrl_width => g_ctrl_width,
g_page_size => g_page_size,
g_packet_mem_multiply => g_packet_mem_multiply
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
......@@ -545,7 +556,7 @@ architecture rtl of swc_core is
generic map(
g_page_addr_width => c_page_addr_width,
g_prio_width => c_prio_width,
g_max_pck_size_width => g_max_pck_size_width,
g_max_pck_size_width => c_max_pck_size_width,
g_num_ports => g_num_ports
)
port map(
......
modules/wrsw_swcore/swc_multiport_page_allocator.vhd
View file @ 6cffb99a
......@@ -168,6 +168,7 @@ begin -- syn
generic map (
g_num_pages => g_page_num,
g_page_addr_width=> g_page_addr_width,
g_num_ports => g_page_num,
g_usecount_width => g_usecount_width)
port map (
clk_i => clk_i,
......
modules/wrsw_swcore/swc_ob_prio_queue.vhd
View file @ 6cffb99a
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-03
-- Last update: 2010-11-03
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -35,7 +35,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-11-09 1.0 mlipinsk created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -47,7 +47,9 @@ use work.swc_swcore_pkg.all;
entity swc_ob_prio_queue is
generic(
g_per_prio_fifo_size_width : integer --:= c_swc_output_fifo_addr_width
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -67,8 +69,8 @@ entity swc_ob_prio_queue is
-------------------------------------------------------------------------------
wr_en_o : out std_logic;
wr_addr_o : out std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
rd_addr_o : out std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0)
wr_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
rd_addr_o : out std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0)
);
end swc_ob_prio_queue;
......@@ -76,8 +78,8 @@ end swc_ob_prio_queue;
architecture behavoural of swc_ob_prio_queue is
signal head : std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
signal tail : std_logic_vector(c_swc_output_fifo_addr_width - 1 downto 0);
signal head : std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
signal tail : std_logic_vector(g_per_prio_fifo_size_width - 1 downto 0);
signal not_full : std_logic;
signal not_empty : std_logic;
......
modules/wrsw_swcore/swc_output_block.vhd
View file @ 6cffb99a
......@@ -273,6 +273,9 @@ begin -- behavoural
read(i) <= read_array(i) when (state = SET_PAGE) else '0';--rx_dreq_i;
PRIO_QUEUE_CTRL : swc_ob_prio_queue
generic map(
g_per_prio_fifo_size_width => c_swc_output_fifo_addr_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
modules/wrsw_swcore/swc_packet_mem.vhd
View file @ 6cffb99a
This diff is collapsed.
modules/wrsw_swcore/swc_page_alloc_old.vhd
View file @ 6cffb99a
......@@ -109,6 +109,8 @@ entity swc_page_allocator is
-- number of bits of the page address
g_page_addr_width: integer := 11; --g_page_addr_bits
g_num_ports : integer ;--:= c_swc_num_ports
-- number of bits of the user count value
g_usecount_width: integer := 4 --g_use_count_bits
);
......@@ -397,7 +399,7 @@ begin -- syn
-- ========= hystheresis ===========================
if(nomem = '0' and (free_blocks < 3)) then
nomem <= '1';
elsif(nomem = '1' and (free_blocks > (3*c_swc_num_ports))) then
elsif(nomem = '1' and (free_blocks > (3*g_num_ports))) then
nomem <= '0';
end if;
-- ========= =========== ===========================
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 6cffb99a
This diff is collapsed.
modules/wrsw_swcore/xswc_core.vhd
View file @ 6cffb99a
......@@ -53,7 +53,7 @@ use work.wrsw_shared_types_pkg.all;
entity xswc_core is
generic
(
g_num_ports : integer := c_swc_num_ports
g_num_ports : integer := 7 --c_swc_num_ports
);
port (
clk_i : in std_logic;
......@@ -66,14 +66,12 @@ entity xswc_core is
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
......@@ -92,7 +90,7 @@ architecture rtl of xswc_core is
g_mem_size : integer ;--:= c_swc_packet_mem_size
g_page_size : integer ;--:= c_swc_page_size
g_prio_num : integer ;--:= c_swc_output_prio_num;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
......@@ -117,7 +115,6 @@ architecture rtl of xswc_core is
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
......@@ -135,30 +132,24 @@ architecture rtl of xswc_core is
);
end component;
begin
U_swc_core: swc_core
generic map(
g_mem_size => c_swc_packet_mem_size,
g_page_size => c_swc_page_size,
g_prio_num => c_swc_output_prio_num,
g_max_pck_size_width => c_swc_max_pck_size_width,
g_num_ports => c_swc_num_ports,
g_data_width => c_swc_data_width,
g_ctrl_width => c_swc_ctrl_width,
g_pck_pg_free_fifo_size => c_swc_freeing_fifo_size,
g_input_block_cannot_accept_data => "drop_pck", --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_output_block_per_prio_fifo_size => c_swc_output_fifo_size,
g_mem_size => 65536, -- c_swc_packet_mem_size,
g_page_size => 64, -- c_swc_page_size,
g_prio_num => 8, -- c_swc_output_prio_num,
g_max_pck_size => 10 * 1024, --10kB -- c_swc_max_pck_size,
g_num_ports => 7 , -- c_swc_num_ports,
g_data_width => 16, -- c_swc_data_width,
g_ctrl_width => 4, -- c_swc_ctrl_width,
g_pck_pg_free_fifo_size => (65536/64)/2, -- c_swc_freeing_fifo_size,
g_input_block_cannot_accept_data => "drop_pck", --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_output_block_per_prio_fifo_size => 64, -- c_swc_output_fifo_size,
-- probably useless with new memory
g_packet_mem_multiply => c_swc_packet_mem_multiply,
g_input_block_fifo_size => c_swc_input_fifo_size,
g_input_block_fifo_full_in_advance => c_swc_fifo_full_in_advance
g_packet_mem_multiply => 16, -- c_swc_packet_mem_multiply,
g_input_block_fifo_size => 2 * 16, -- c_swc_input_fifo_size,
g_input_block_fifo_full_in_advance => (2 * 16) - 3 -- c_swc_fifo_full_in_advance
)
port map (
clk_i => clk_i,
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ 6cffb99a
......@@ -291,6 +291,9 @@ begin -- behavoural
read(i) <= read_array(i) when (state = SET_PAGE) else '0';--rx_dreq_i;
PRIO_QUEUE_CTRL : swc_ob_prio_queue
generic map(
g_per_prio_fifo_size_width => c_per_prio_fifo_size_width -- c_swc_output_fifo_addr_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
......
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