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Commit 9797d04d authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-azing]: intermediate backup: allocator and lsot dealocator done

parent d346afae
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Showing with 359 additions and 273 deletions
modules/wrsw_swcore/Manifest.py
View file @ 9797d04d
......@@ -12,7 +12,7 @@ files = [
"swc_block_alloc.vhd",
"swc_core.vhd",
"swc_input_block.vhd",
"swc_lost_pck_dealloc.vhd",
#"swc_lost_pck_dealloc.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
"swc_multiport_pck_pg_free_module.vhd",
......
modules/wrsw_swcore/swc_core.vhd
View file @ 9797d04d
This diff is collapsed.
modules/wrsw_swcore/swc_lost_pck_dealloc.vhd
View file @ 9797d04d
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2011-03-15
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -37,6 +37,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-11-15 1.0 mlipinsk Created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
......@@ -47,32 +48,34 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
--use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
entity swc_lost_pck_dealloc is
generic (
g_page_addr_width : integer --:= c_swc_page_addr_width;
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic;
ob_force_free_done_o : out std_logic;
ob_force_free_pgaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ob_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_page_addr_width -1 downto 0)
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
);
......@@ -96,20 +99,20 @@ architecture syn of swc_lost_pck_dealloc is
signal ob_force_free_done : std_logic;
signal fifo_wr : std_logic;
signal fifo_data_in : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal fifo_data_in : std_logic_vector(g_page_addr_width - 1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_data_out : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal fifo_data_out : std_logic_vector(g_page_addr_width - 1 downto 0);
signal fifo_rd : std_logic;
signal fifo_clean : std_logic;
signal current_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal current_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal ll_read_req : std_logic;
signal mmu_force_free : std_logic;
signal ones : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal ones : std_logic_vector(g_page_addr_width - 1 downto 0);
......@@ -161,7 +164,7 @@ begin -- syn
U_FIFO: generic_sync_fifo
generic map(
g_data_width => c_swc_page_addr_width,
g_data_width => g_page_addr_width,
g_size => 16
)
port map (
......
modules/wrsw_swcore/swc_multiport_lost_pck_dealloc.vhd
View file @ 9797d04d
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-13
-- Last update: 2010-11-13
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -35,6 +35,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-11-13 1.0 mlipinsk Created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
......@@ -48,27 +49,31 @@ use work.swc_swcore_pkg.all;
entity swc_multiport_lost_pck_dealloc is
generic (
g_num_ports : integer --:= c_swc_num_ports
g_page_addr_width : integer --:= c_swc_page_addr_width;
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ob_force_free_done_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ob_force_free_pgaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ob_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ob_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
--ll_read_data_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(c_swc_num_ports * c_swc_page_addr_width -1 downto 0)
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
);
end swc_multiport_lost_pck_dealloc;
......@@ -80,7 +85,7 @@ begin -- syn
lpd_gen : for i in 0 to c_swc_num_ports-1 generate
lpd_gen : for i in 0 to g_num_ports-1 generate
LPD: swc_lost_pck_dealloc
port map(
......@@ -89,21 +94,21 @@ begin -- syn
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ob_force_free_i => ob_force_free_i(i),
ob_force_free_done_o => ob_force_free_done_o(i),
ob_force_free_pgaddr_i => ob_force_free_pgaddr_i((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
ob_force_free_pgaddr_i => ob_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width),
--ll_read_data_i => ll_read_data_i((i+1)*c_swc_num_ports - 1 downto i * c_swc_num_ports),
ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
--ll_read_data_i => ll_read_data_i((i+1)*g_num_ports - 1 downto i * g_num_ports),
ll_read_data_i => ll_read_data_i,
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*c_swc_page_addr_width - 1 downto i * c_swc_page_addr_width)
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width)
);
......
modules/wrsw_swcore/swc_page_alloc.vhd
View file @ 9797d04d
......@@ -107,10 +107,10 @@ entity swc_page_allocator_new is
g_num_pages : integer := 2048;
-- number of bits of the page address
g_page_addr_bits : integer := 11;
g_page_addr_width: integer := 11; --g_page_addr_bits
-- number of bits of the user count value
g_use_count_bits : integer := 4
g_usecount_width: integer := 4 --g_usecount_width
);
port (
......@@ -149,11 +149,11 @@ entity swc_page_allocator_new is
-- "Use count" value for the page to be allocated. If the page is to be
-- used by multiple output queues, each of them will attempt to free it.
usecnt_i : in std_logic_vector(g_use_count_bits-1 downto 0);
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
......@@ -173,25 +173,25 @@ architecture syn of swc_page_allocator_new is
signal nomem : std_logic;
signal rd_ptr, wr_ptr : unsigned(g_page_addr_bits-1 downto 0);
signal free_pages : unsigned(g_page_addr_bits downto 0);
signal rd_ptr, wr_ptr : unsigned(g_page_addr_width-1 downto 0);
signal free_pages : unsigned(g_page_addr_width downto 0);
signal q_write , q_read : std_logic;
signal pending_free : std_logic;
signal read_usecnt : std_logic_vector(g_use_count_bits-1 downto 0);
signal q_init_data : unsigned(g_page_addr_bits -1 downto 0);
signal read_usecnt : std_logic_vector(g_usecount_width-1 downto 0);
signal q_init_data : unsigned(g_page_addr_width -1 downto 0);
signal initializing : std_logic;
signal usecnt_write : std_logic;
signal usecnt_addr : std_logic_vector(g_page_addr_bits-1 downto 0);
signal usecnt_rddata, usecnt_wrdata : std_logic_vector(g_use_count_bits-1 downto 0);
signal usecnt_addr : std_logic_vector(g_page_addr_width-1 downto 0);
signal usecnt_rddata, usecnt_wrdata : std_logic_vector(g_usecount_width-1 downto 0);
signal q_output_addr : std_logic_vector(g_page_addr_bits-1 downto 0);
signal q_output_addr : std_logic_vector(g_page_addr_width-1 downto 0);
signal alloc_d0 : std_logic;
signal free_d0 : std_logic;
signal done_int : std_logic;
signal ram_ones : std_logic_vector(g_page_addr_bits + g_use_count_bits -1 downto 0);
signal ram_ones : std_logic_vector(g_page_addr_width + g_usecount_width -1 downto 0);
......@@ -200,20 +200,20 @@ ram_ones <=(others => '1');
U_Queue_RAM : generic_dpram
generic map (
g_data_width => g_page_addr_bits,
g_size => 2**g_page_addr_bits,
g_data_width => g_page_addr_width,
g_size => 2**g_page_addr_width,
g_with_byte_enable => false,
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => ram_ones((g_page_addr_bits+7)/8 - 1 downto 0),
bwea_i => ram_ones((g_page_addr_width+7)/8 - 1 downto 0),
wea_i => q_write,
aa_i => std_logic_vector(wr_ptr),
da_i => pgaddr_i,
clkb_i => clk_i,
bweb_i => ram_ones((g_page_addr_bits+7)/8 - 1 downto 0),
bweb_i => ram_ones((g_page_addr_width+7)/8 - 1 downto 0),
web_i => initializing,
ab_i => std_logic_vector(rd_ptr),
db_i => std_logic_vector(rd_ptr),
......@@ -225,30 +225,30 @@ ram_ones <=(others => '1');
usecnt_write <= (alloc_d0 or set_usecnt_i or free_d0 or force_free_i) and not initializing;
usecnt_wrdata <= usecnt_i when (set_usecnt_i = '1' or alloc_d0 = '1') else
f_gen_dummy_vec('0', g_use_count_bits) when force_free_i = '1' else
f_gen_dummy_vec('0', g_usecount_width) when force_free_i = '1' else
std_logic_vector(unsigned(usecnt_rddata) - 1);
U_UseCnt_RAM : generic_dpram
generic map (
g_data_width => g_use_count_bits,
g_size => 2**g_page_addr_bits,
g_data_width => g_usecount_width,
g_size => 2**g_page_addr_width,
g_with_byte_enable => false,
g_dual_clock => false)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
wea_i => usecnt_write,
bwea_i => ram_ones((g_use_count_bits+7)/8 - 1 downto 0),
bwea_i => ram_ones((g_usecount_width+7)/8 - 1 downto 0),
aa_i => usecnt_addr,
da_i => usecnt_wrdata,
qa_o => usecnt_rddata,
clkb_i => clk_i,
bweb_i => ram_ones((g_use_count_bits+7)/8 - 1 downto 0),
bweb_i => ram_ones((g_usecount_width+7)/8 - 1 downto 0),
web_i => initializing,
ab_i => std_logic_vector(rd_ptr),
db_i => f_gen_dummy_vec('0', g_use_count_bits));
db_i => f_gen_dummy_vec('0', g_usecount_width));
p_pointers : process(clk_i)
begin
......
modules/wrsw_swcore/swc_page_alloc_old.vhd
View file @ 9797d04d
......@@ -107,10 +107,10 @@ entity swc_page_allocator is
g_num_pages : integer := 2048;
-- number of bits of the page address
g_page_addr_bits : integer := 11;
g_page_addr_width: integer := 11; --g_page_addr_bits
-- number of bits of the user count value
g_use_count_bits : integer := 4
g_usecount_width: integer := 4 --g_use_count_bits
);
port (
......@@ -149,11 +149,11 @@ entity swc_page_allocator is
-- "Use count" value for the page to be allocated. If the page is to be
-- used by multiple output queues, each of them will attempt to free it.
usecnt_i : in std_logic_vector(g_use_count_bits-1 downto 0);
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
......@@ -187,7 +187,7 @@ architecture syn of swc_page_allocator is
constant c_l1_bitmap_size : integer := g_num_pages/32;
constant c_l1_bitmap_addrbits : integer := g_page_addr_bits - 5;
constant c_l1_bitmap_addrbits : integer := g_page_addr_width - 5;
type t_state is (IDLE, ALLOC_LOOKUP_L1, ALLOC_LOOKUP_L0_UPDATE,
FREE_CHECK_USECNT, FREE_RELEASE_PAGE, FREE_DECREASE_UCNT,
......@@ -210,7 +210,7 @@ architecture syn of swc_page_allocator is
signal state : t_state;
signal free_blocks : unsigned(g_page_addr_bits downto 0);
signal free_blocks : unsigned(g_page_addr_width downto 0);
-- address decoded from l1_bitmap, we read data from this address
-- to decode the low part of the page address
......@@ -219,19 +219,19 @@ architecture syn of swc_page_allocator is
signal l0_wr : std_logic;
-- this is used for storing user count
signal usecnt_mem_wraddr : std_logic_vector(g_page_addr_bits-1 downto 0);
signal usecnt_mem_rdaddr : std_logic_vector(g_page_addr_bits-1 downto 0);
signal usecnt_mem_wraddr : std_logic_vector(g_page_addr_width-1 downto 0);
signal usecnt_mem_rdaddr : std_logic_vector(g_page_addr_width-1 downto 0);
signal usecnt_mem_wr : std_logic;
signal usecnt_mem_rddata : std_logic_vector(g_use_count_bits-1 downto 0);
signal usecnt_mem_wrdata : std_logic_vector(g_use_count_bits-1 downto 0);
signal usecnt_mem_rddata : std_logic_vector(g_usecount_width-1 downto 0);
signal usecnt_mem_wrdata : std_logic_vector(g_usecount_width-1 downto 0);
signal pgaddr_to_free : std_logic_vector(g_page_addr_bits -1 downto 0);
signal pgaddr_to_free : std_logic_vector(g_page_addr_width -1 downto 0);
signal page_freeing_in_last_operation : std_logic;
signal previously_freed_page : std_logic_vector(g_page_addr_bits -1 downto 0);
signal previously_freed_page : std_logic_vector(g_page_addr_width -1 downto 0);
signal tmp_page : std_logic_vector(g_page_addr_bits -1 downto 0);
signal tmp_page : std_logic_vector(g_page_addr_width -1 downto 0);
-- signal tmp_pgs : std_logic_vector(1023 downto 0);
......@@ -297,8 +297,8 @@ begin -- syn
L0_UCNTMEM : generic_dpram
generic map (
g_data_width => g_use_count_bits,
-- g_addr_bits => g_page_addr_bits,
g_data_width => g_usecount_width,
-- g_addr_bits => g_page_addr_width,
g_size => g_num_pages)
port map (
clka_i => clk_i,
......@@ -308,12 +308,12 @@ begin -- syn
aa_i => usecnt_mem_wraddr,
qa_o => open,
wea_i => usecnt_mem_wr,
bwea_i => ones((g_use_count_bits+7)/8 -1 downto 0),--ones((g_use_count_bits+7)/8 -1 downto 0),
bwea_i => ones((g_usecount_width+7)/8 -1 downto 0),--ones((g_usecount_width+7)/8 -1 downto 0),
ab_i => usecnt_mem_rdaddr,
qb_o => usecnt_mem_rddata,
db_i => ones(g_use_count_bits-1 downto 0),
bweb_i => ones((g_use_count_bits+7)/8-1 downto 0), --ones((g_use_count_bits+7)/8-1 downto 0),
db_i => ones(g_usecount_width-1 downto 0),
bweb_i => ones((g_usecount_width+7)/8-1 downto 0), --ones((g_usecount_width+7)/8-1 downto 0),
web_i => '0'
);
......@@ -432,8 +432,8 @@ begin -- syn
state <= FREE_CHECK_USECNT;
-- decoding of provided code into low and high part
l0_wr_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_wr_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
done_o <= '1'; -- assert the done signal early enough
......@@ -456,8 +456,8 @@ begin -- syn
state <= DUMMY; -- FREE_RELEASE_PAGE;
-- decoding of provided code into low and high part
l0_wr_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_wr_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
done_o <= '1'; -- assert the done signal early enough
......@@ -489,8 +489,8 @@ begin -- syn
state <= FREE_CHECK_USECNT;
-- decoding of provided code into low and high part
l0_wr_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_bits-1 downto 5);
l0_wr_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
l0_rd_addr <= pgaddr_i(g_page_addr_width-1 downto 5);
--usecnt_mem_rdaddr <= pgaddr_i;
usecnt_mem_wraddr <= pgaddr_i;
done_o <= '1'; -- assert the done signal early enough
......@@ -565,8 +565,8 @@ begin -- syn
l0_wr_data <= l0_rd_data or f_onehot_decode(pgaddr_to_free(4 downto 0));
l0_wr <= '1';
l1_bitmap <= l1_bitmap or f_onehot_decode(pgaddr_to_free(g_page_addr_bits-1 downto 5));
-- l1_bitmap <= l1_bitmap or f_onehot_decode(pgaddr_i(g_page_addr_bits-1 downto 5));
l1_bitmap <= l1_bitmap or f_onehot_decode(pgaddr_to_free(g_page_addr_width-1 downto 5));
-- l1_bitmap <= l1_bitmap or f_onehot_decode(pgaddr_i(g_page_addr_width-1 downto 5));
free_blocks <= free_blocks+ 1;
usecnt_mem_wrdata <= (others => '0');
usecnt_mem_wr <= '1';
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 9797d04d
......@@ -124,8 +124,8 @@ package swc_swcore_pkg is
component swc_page_allocator
generic (
g_num_pages : integer;
g_page_addr_bits : integer;
g_use_count_bits : integer);
g_page_addr_width : integer;
g_usecount_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -133,9 +133,9 @@ package swc_swcore_pkg is
free_i : in std_logic;
force_free_i : in std_logic;
set_usecnt_i : in std_logic;
usecnt_i : in std_logic_vector(g_use_count_bits-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_bits -1 downto 0);
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
done_o : out std_logic;
......@@ -146,8 +146,8 @@ package swc_swcore_pkg is
component swc_page_allocator_new
generic (
g_num_pages : integer;
g_page_addr_bits : integer;
g_use_count_bits : integer);
g_page_addr_width : integer;
g_usecount_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -155,9 +155,9 @@ package swc_swcore_pkg is
free_i : in std_logic;
force_free_i : in std_logic;
set_usecnt_i : in std_logic;
usecnt_i : in std_logic_vector(g_use_count_bits-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_bits -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_bits -1 downto 0);
usecnt_i : in std_logic_vector(g_usecount_width-1 downto 0);
pgaddr_i : in std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
pgaddr_valid_o : out std_logic;
idle_o : out std_logic;
done_o : out std_logic;
......@@ -221,6 +221,11 @@ package swc_swcore_pkg is
end component;
component swc_multiport_linked_list is
generic (
g_num_ports : integer; --:= c_swc_num_ports
g_page_addr_width : integer; --:= c_swc_page_addr_width;
g_page_num : integer --:= c_swc_packet_mem_num_pages
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -386,6 +391,12 @@ package swc_swcore_pkg is
component swc_multiport_page_allocator is
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_page_num : integer ;--:= c_swc_packet_mem_num_pages
g_usecount_width : integer --:= c_swc_usecount_width
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -547,7 +558,15 @@ package swc_swcore_pkg is
end component;
component xswc_output_block is
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_output_block_per_prio_fifo_size : integer ;--:= c_swc_output_fifo_size
g_prio_width : integer ;--:= c_swc_prio_width;, c_swc_output_prio_num_width
g_prio_num : integer --:= c_swc_output_prio_num
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -676,6 +695,7 @@ component swc_multiport_pck_pg_free_module is
);
end component;
end swc_swcore_pkg;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 9797d04d
......@@ -89,18 +89,22 @@ architecture rtl of xswc_core is
component swc_core is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_prio_width : integer ;--:= c_swc_prio_width;
g_mem_size : integer ;--:= c_swc_packet_mem_size
g_page_size : integer ;--:= c_swc_page_size
g_prio_num : integer ;--:= c_swc_output_prio_num;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_output_block_per_prio_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
);
port (
clk_i : in std_logic;
......@@ -141,14 +145,17 @@ begin
U_swc_core: swc_core
generic map(
g_page_addr_width => c_swc_page_addr_width,
g_prio_width => c_swc_prio_width,
g_mem_size => c_swc_packet_mem_size,
g_page_size => c_swc_page_size,
g_prio_num => c_swc_output_prio_num,
g_max_pck_size_width => c_swc_max_pck_size_width,
g_num_ports => c_swc_num_ports,
g_data_width => c_swc_data_width,
g_ctrl_width => c_swc_ctrl_width,
g_pck_pg_free_fifo_size => c_swc_freeing_fifo_size,
g_input_block_cannot_accept_data => "drop_pck", --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_output_block_per_prio_fifo_size => c_swc_output_fifo_size,
-- probably useless with new memory
g_packet_mem_multiply => c_swc_packet_mem_multiply,
g_input_block_fifo_size => c_swc_input_fifo_size,
g_input_block_fifo_full_in_advance => c_swc_fifo_full_in_advance
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ 9797d04d
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