hdl: platform: updated Altera libraries

7b0f741e · Tomasz Wlostowski · 2f477723 · 7b0f741e · 7b0f741e
Commit 7b0f741e authored Dec 07, 2010 by Tomasz Wlostowski
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Showing with 10 additions and 3 deletions

generic_ssram_dualport_singleclock.vhd generic_ssram_dualport_singleclock.vhd +8 -2

platform_specific.vhd platform_specific.vhd +2 -1

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--- a/generic_ssram_dualport_singleclock.vhd
+++ b/generic_ssram_dualport_singleclock.vhd
@@ -43,7 +43,9 @@ entity generic_ssram_dualport_singleclock is
  generic (
    g_width     : natural := 8;
    g_addr_bits : natural := 10;
-    g_size      : natural := 1024);
+    g_size      : natural := 1024;
+    g_init_file : string  := "UNUSED");
  port
    (
      data_i    : in  std_logic_vector (g_width-1 downto 0);
@@ -80,6 +82,8 @@ architecture SYN of generic_ssram_dualport_singleclock is
      widthad_b                          : natural;
      width_a                            : natural;
      width_b                            : natural;
+      INIT_FILE                          : string ;
      width_byteena_a                    : natural
      );
    port (
@@ -115,7 +119,9 @@ begin
      widthad_b                          => g_addr_bits,
      width_a                            => g_width,
      width_b                            => g_width,
-      width_byteena_a                    => 1
+      width_byteena_a                    => 1,
+      INIT_FILE => g_init_file
      )
    port map (
      wren_a    => wr_en_i,

--- a/platform_specific.vhd
+++ b/platform_specific.vhd
@@ -68,7 +68,8 @@ package platform_specific is
    generic (
      g_width     : natural;
      g_addr_bits : natural;
-      g_size      : natural);
+      g_size      : natural;
+      g_init_file : string := "UNUSED");
    port (
      data_i    : in  std_logic_vector (g_width-1 downto 0);
      clk_i     : in  std_logic;