swcore: multiport LL rewritten to use multiport RAM with 2 write ports

8452ca3a · Grzegorz Daniluk · 68dda3e8 · 8452ca3a
Commit 8452ca3a authored Sep 03, 2016 by Grzegorz Daniluk
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swc_multiport_linked_list.vhd modules/wrsw_swcore/swc_multiport_linked_list.vhd +247 -233

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--- a/modules/wrsw_swcore/swc_multiport_linked_list.vhd
+++ b/modules/wrsw_swcore/swc_multiport_linked_list.vhd