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Commit 8b65c022 authored by Maciej Lipinski's avatar Maciej Lipinski
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RTU-bugfix: aging_bug-related two changes 1) the source entry search in HTAB is… 

RTU-bugfix: aging_bug-related two changes 1) the source entry search in HTAB is considered successful only if the found port_dst_mask matches the search-requesting port; 2) updating aging table only on source MAC found. No changes for destination MAC lookup
parent b22883d8
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Showing with 52 additions and 4 deletions
modules/wrsw_rtu/rtu_lookup_engine.vhd
View file @ 8b65c022
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-22
-- Last update: 2012-06-28
-- Last update: 2013-03-24
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -35,6 +35,7 @@
-- Revisions :
-- Date Version Author Description
-- 2010-05-22 1.0 lipinskimm Created
-- 2013-03-24 1.1 lipinskimm aging-related bugfix
-------------------------------------------------------------------------------
......@@ -49,6 +50,7 @@ use work.genram_pkg.all;
entity rtu_lookup_engine is
generic(
g_num_ports : integer;
g_hash_size : integer := 11);
port(
......@@ -90,6 +92,14 @@ entity rtu_lookup_engine is
-- indicates that the search has been finished (whether the entry was found or not)
drdy_o : out std_logic;
-- mask indicating the source of request (on which port the frame was received)
port_i : in std_logic_vector(g_num_ports -1 downto 0); -- ML (24/03/2013): aging bugfix
-- indicates whetehr the sarch concenrs
-- 0: source MAC
-- 1: destination MAC
src_dst_i : in std_logic; -- ML (24/03/2013): aging bugfix
-------------------------------------------------------------------------------
-- read data
-------------------------------------------------------------------------------
......@@ -220,11 +230,22 @@ begin
when NEXT_BUCKET =>
-- got a match?
if(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i) then
-- ML (24/03/2013): aging bugfix --------------------------------------------------
if(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i and
src_dst_i = '0' and -- this is source MAC => need to check that it's been received
-- on the correct port:
(cur_entry.port_mask_dst(g_num_ports-1 downto 0) and port_i) = port_i) then
drdy_o <= '1';
found_o <= '1';
entry_o <= cur_entry;
lookup_state <= OUTPUT_RESULT;
elsif(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i and
src_dst_i = '1') then -- this is destination MAC search,
drdy_o <= '1';
found_o <= '1';
entry_o <= cur_entry;
lookup_state <= OUTPUT_RESULT;
------------------------------------------------------------------------------------
elsif(bucket_entry = "00" or cur_entry.valid = '0') then
drdy_o <= '1';
found_o <= '0';
......
modules/wrsw_rtu/rtu_match.vhd
View file @ 8b65c022
......@@ -40,6 +40,7 @@
-- Date Version Author Description
-- 2010-05-08 1.0 lipinskimm Created
-- 2010-05-22 1.1 lipinskimm revised, developed further
-- 2013-03-24 1.2 lipinskimm aging bugfix
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
......@@ -98,6 +99,8 @@ entity rtu_match is
htab_fid_o : out std_logic_vector(c_wrsw_fid_width - 1 downto 0);
htab_drdy_i : in std_logic;
htab_entry_i : in t_rtu_htab_entry;
htab_port_o : out std_logic_vector(g_num_ports-1 downto 0); -- ML (24/03/2013): aging bugfix
htab_src_dst_o:out std_logic; -- ML (24/03/2013): aging bugfix
-------------------------------------------------------------------------------
-- Unrecongized FIFO (operated by WB)
......@@ -670,14 +673,21 @@ begin
-- update aging aram (in any case that entry was found,
-- even if dropped later, we update aging aram
s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
s_aram_main_wr <= '1';
-- ML (24/03/2013): aging bugfix : update aging only for destination found
-- s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
-- s_aram_main_wr <= '1';
----------------------------------------------------------------------------
-- SOURCE MAC ENTRY SEARCH
----------------------------------------------------------------------------
if(s_src_dst_sel = '0') then
-- ML (24/03/2013): aging bugfix : update aging only for destination found
-- update aging aram (in any case that entry was found,
-- even if dropped later, we update aging aram
s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
s_aram_main_wr <= '1';
-------------------------------------------
-- source MAC address is blocked? -
-- drop the package
......@@ -1165,5 +1175,8 @@ begin
rsp_fifo_output_o <= s_rsp_dst_port_mask & s_rsp_drop & s_rsp_prio & s_port_id;
htab_src_dst_o <= s_src_dst_sel; -- ML (24/03/2013): aging bugfix
htab_port_o <= s_port_id; -- ML (24/03/2013): aging bugfix
end architecture;
modules/wrsw_rtu/rtu_private_pkg.vhd
View file @ 8b65c022
......@@ -211,6 +211,7 @@ package rtu_private_pkg is
component rtu_lookup_engine
generic (
g_num_ports : integer;
g_hash_size : integer := c_wrsw_hash_width);
port (
clk_match_i : in std_logic;
......@@ -229,6 +230,8 @@ package rtu_private_pkg is
mac_i : in std_logic_vector(c_wrsw_mac_addr_width -1 downto 0);
fid_i : in std_logic_vector(c_wrsw_fid_width - 1 downto 0);
drdy_o : out std_logic;
port_i : in std_logic_vector(g_num_ports -1 downto 0); -- ML (24/03/2013): aging bugfix
src_dst_i : in std_logic; -- ML (24/03/2013): aging bugfix
entry_o : out t_rtu_htab_entry);
end component;
......@@ -264,6 +267,8 @@ package rtu_private_pkg is
htab_fid_o : out std_logic_vector(c_wrsw_fid_width - 1 downto 0);
htab_drdy_i : in std_logic;
htab_entry_i : in t_rtu_htab_entry;
htab_port_o : out std_logic_vector(g_num_ports-1 downto 0); -- ML (24/03/2013): aging bugfix
htab_src_dst_o : out std_logic; -- ML (24/03/2013): aging bugfix
rtu_ufifo_wr_req_o : out std_logic;
rtu_ufifo_wr_full_i : in std_logic;
rtu_ufifo_wr_empty_i : in std_logic;
......
modules/wrsw_rtu/wrsw_rtu.vhd
View file @ 8b65c022
......@@ -315,6 +315,9 @@ architecture behavioral of wrsw_rtu is
signal current_pcr : integer;
signal htab_port : std_logic_vector(g_num_ports - 1 downto 0);
signal htab_src_dst : std_logic;
function f_slice (
x : std_logic_vector;
index : integer;
......@@ -482,6 +485,8 @@ begin
htab_fid_o => htab_fid,
htab_drdy_i => htab_drdy,
htab_entry_i => htab_entry,
htab_port_o => htab_port, -- ML (24/03/2013): aging bugfix
htab_src_dst_o => htab_src_dst, -- ML (24/03/2013): aging bugfix
rtu_ufifo_wr_req_o => regs_towb.ufifo_wr_req_i,
rtu_ufifo_wr_full_i => regs_fromwb.ufifo_wr_full_o,
......@@ -519,6 +524,8 @@ begin
mfifo_trigger <= regs_fromwb.gcr_mfifotrig_o and regs_fromwb.gcr_mfifotrig_load_o;
U_Lookup : rtu_lookup_engine
generic map (
g_num_ports => g_num_ports)
port map (
clk_sys_i => clk_sys_i,
clk_match_i => clk_sys_i,
......@@ -538,6 +545,8 @@ begin
mac_i => htab_mac,
fid_i => htab_fid,
drdy_o => htab_drdy,
port_i => htab_port, -- ML (24/03/2013): aging bugfix
src_dst_i => htab_src_dst, -- ML (24/03/2013): aging bugfix
entry_o => htab_entry
);
......
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