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White Rabbit Switch - Gateware
Commit 90536db3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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add _ljd_ prefix to everything Low-Jitter Daughterboard related

parent f8127017
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Showing with 267 additions and 262 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 90536db3
...@@ -129,20 +129,19 @@ entity wrsw_rt_subsystem is ...@@ -129,20 +129,19 @@ entity wrsw_rt_subsystem is
------------------------------------------------------ ------------------------------------------------------
-- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
------------------------------------------------------ ------------------------------------------------------
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic := '0';
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0');
-- LJD AD9516
-- AD9516 ljd_pll_mosi_o : out std_logic;
ext_pll_mosi_o : out std_logic; ljd_pll_miso_i : in std_logic;
ext_pll_miso_i : in std_logic; ljd_pll_sck_o : out std_logic;
ext_pll_sck_o : out std_logic; ljd_pll_cs_n_o : out std_logic;
ext_pll_cs_n_o : out std_logic; ljd_pll_sync_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic; ljd_pll_reset_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-- Debug -- Debug
spll_dbg_o : out std_logic_vector(5 downto 0) spll_dbg_o : out std_logic_vector(5 downto 0)
...@@ -439,10 +438,10 @@ begin -- rtl ...@@ -439,10 +438,10 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_SPI_EXT), slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT), slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open, desc_o => open,
pad_cs_o(0) => ext_pll_cs_n_o, pad_cs_o(0) => ljd_pll_cs_n_o,
pad_sclk_o => ext_pll_sck_o, pad_sclk_o => ljd_pll_sck_o,
pad_mosi_o => ext_pll_mosi_o, pad_mosi_o => ljd_pll_mosi_o,
pad_miso_i => ext_pll_miso_i); pad_miso_i => ljd_pll_miso_i);
U_GPIO : xwb_gpio_port U_GPIO : xwb_gpio_port
generic map ( generic map (
...@@ -496,9 +495,9 @@ begin -- rtl ...@@ -496,9 +495,9 @@ begin -- rtl
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i; cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3); rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4); ljd_pll_reset_n_o <= gpio_out(4);
gpio_in(5) <= ljd_board_detected; gpio_in(5) <= ljd_board_detected;
gpio_in(8 downto 6) <= ext_board_osc_freq_i; gpio_in(8 downto 6) <= ljd_osc_freq_i;
U_Main_DAC : gc_serial_dac U_Main_DAC : gc_serial_dac
...@@ -538,23 +537,23 @@ begin -- rtl ...@@ -538,23 +537,23 @@ begin -- rtl
------------------------------------------------------ ------------------------------------------------------
-- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
------------------------------------------------------ ------------------------------------------------------
ext_board_clk1_en <= '1'; ljd_clk1_en <= '1';
ext_board_clk2_en <= '1'; ljd_clk2_en <= '1';
ext_pll_sync_n_o <= '1'; ljd_pll_sync_n_o <= '1';
-- Detect the external board (WRS Low jitter daughterboard) -- Detect the Low Jitter Daughterboard
ext_board_checker_inst : entity work.wrsw_ljd_detect ljd_detect_inst : entity work.wrsw_ljd_detect
generic map ( generic map (
g_clk_divider => 16, g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D") g_pattern => x"CAFED00DCAFED00D")
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i, rst_n_i => rst_sys_n_i,
loopback_i => ext_board_loopback_i, loopback_i => ljd_loopback_i,
loopback_o => ext_board_loopback_o, loopback_o => ljd_loopback_o,
board_detected_o => ljd_board_detected); board_detected_o => ljd_board_detected);
ext_board_detected_o <= ljd_board_detected; ljd_detected_o <= ljd_board_detected;
end rtl; end rtl;
top/bare_top/scb_top_bare.vhd
View file @ 90536db3
...@@ -117,18 +117,6 @@ entity scb_top_bare is ...@@ -117,18 +117,6 @@ entity scb_top_bare is
dac_main_sclk_o : out std_logic; dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
-- WRS Low jitter daughterboard (db) external clock
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- AD9516 PLL Control signals -- AD9516 PLL Control signals
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -141,16 +129,30 @@ entity scb_top_bare is ...@@ -141,16 +129,30 @@ entity scb_top_bare is
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Low Jitter Daughterboard support
-------------------------------------------------------------------------------
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
ljd_loopback_i : in std_logic;
ljd_loopback_o : out std_logic;
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Misc pins -- Misc pins
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -653,19 +655,18 @@ begin ...@@ -653,19 +655,18 @@ begin
pll_sync_n_o => pll_sync_n_o, pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o, pll_reset_n_o => pll_reset_n_o,
ext_board_loopback_i => ext_board_loopback_i, ljd_loopback_i => ljd_loopback_i,
ext_board_loopback_o => ext_board_loopback_o, ljd_loopback_o => ljd_loopback_o,
ext_board_clk1_en => ext_board_clk1_en, ljd_clk1_en => ljd_clk1_en,
ext_board_clk2_en => ext_board_clk2_en, ljd_clk2_en => ljd_clk2_en,
ext_board_detected_o => ljd_detected, ljd_detected_o => ljd_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i, ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ext_pll_mosi_o => ext_pll_mosi_o, ljd_pll_miso_i => ljd_pll_miso_i,
ext_pll_miso_i => ext_pll_miso_i, ljd_pll_sck_o => ljd_pll_sck_o,
ext_pll_sck_o => ext_pll_sck_o, ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ext_pll_cs_n_o => ext_pll_cs_n_o, ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o, ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
spll_dbg_o => spll_dbg_o); spll_dbg_o => spll_dbg_o);
...@@ -1312,7 +1313,7 @@ begin ...@@ -1312,7 +1313,7 @@ begin
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
ext_board_detected_o <= ljd_detected; ljd_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected -- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data) dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 90536db3
...@@ -253,18 +253,18 @@ package wrsw_components_pkg is ...@@ -253,18 +253,18 @@ package wrsw_components_pkg is
pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic; ljd_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic; ljd_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic; ljd_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic; ljd_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic; ljd_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic); ljd_pll_reset_n_o : out std_logic);
end component; end component;
component chipscope_icon component chipscope_icon
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 90536db3
...@@ -255,18 +255,18 @@ package wrsw_top_pkg is ...@@ -255,18 +255,18 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic; ljd_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic; ljd_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic; ljd_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic; ljd_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic; ljd_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic; ljd_pll_reset_n_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)); spll_dbg_o : out std_logic_vector(5 downto 0));
end component; end component;
...@@ -322,12 +322,18 @@ package wrsw_top_pkg is ...@@ -322,12 +322,18 @@ package wrsw_top_pkg is
ljd_dac_main_sync_n_o : out std_logic; ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic; ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic; ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
pll_status_i : in std_logic; pll_status_i : in std_logic;
pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
pll_miso_i : in std_logic; pll_miso_i : in std_logic;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 90536db3
...@@ -22,22 +22,22 @@ NET "ext_clk_10mhz_n_i" LOC = AG30; ...@@ -22,22 +22,22 @@ NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0; INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1; INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ext_clk_62mhz_p_i" LOC = AN33; NET "ljd_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34; NET "ljd_clk_62mhz_n_i" LOC = AN34;
NET "ext_board_rev_id_i[0]" LOC = AE29; NET "ljd_rev_id_i[0]" LOC = AE29;
NET "ext_board_rev_id_i[1]" LOC = AE28; NET "ljd_rev_id_i[1]" LOC = AE28;
NET "ext_board_rev_id_i[2]" LOC = AM32; NET "ljd_rev_id_i[2]" LOC = AM32;
NET "ext_board_osc_freq_i[0]" LOC = AN32; NET "ljd_osc_freq_i[0]" LOC = AN32;
NET "ext_board_osc_freq_i[1]" LOC = AP33; NET "ljd_osc_freq_i[1]" LOC = AP33;
NET "ext_board_osc_freq_i[2]" LOC = AP32; NET "ljd_osc_freq_i[2]" LOC = AP32;
NET "ext_board_clk1_en" LOC = AL31; NET "ljd_clk1_en" LOC = AL31;
NET "ext_board_clk2_en" LOC = AK31; NET "ljd_clk2_en" LOC = AK31;
NET "ext_board_loopback_i" LOC = AM31; NET "ljd_loopback_i" LOC = AM31;
NET "ext_board_loopback_o" LOC = AL30; NET "ljd_loopback_o" LOC = AL30;
#EBI BUS #EBI BUS
#NET "cpu_clk_i" LOC=""; #NET "cpu_clk_i" LOC="";
...@@ -118,9 +118,9 @@ NET "dac_main_sync_n_o" LOC="AM17"; ...@@ -118,9 +118,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17"; NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17"; NET "dac_main_data_o" LOC="AP17";
NET "ext_dac_main_sync_n_o" LOC = AH32; NET "ljd_dac_main_sync_n_o" LOC = AH32;
NET "ext_dac_main_sclk_o" LOC = AK32; NET "ljd_dac_main_sclk_o" LOC = AK32;
NET "ext_dac_main_data_o" LOC = AK33; NET "ljd_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18"; NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16"; NET "pll_sck_o" LOC="AE16";
...@@ -130,13 +130,13 @@ NET "pll_reset_n_o" LOC="AL16"; ...@@ -130,13 +130,13 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13"; NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18"; NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27; NET "ljd_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26; NET "ljd_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27; NET "ljd_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28; NET "ljd_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29; NET "ljd_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25; NET "ljd_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34; NET "ljd_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11"; NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11"; NET "uart_rxd_i" LOC="D11";
...@@ -334,10 +334,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%; ...@@ -334,10 +334,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i; NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%; TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ext_clk_62mhz_p_i" TNM_NET = "ext_clk_62mhz_p_i"; NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
TIMESPEC TS_ext_clk_62mhz_p_i = PERIOD "ext_clk_62mhz_p_i" 16 ns HIGH 50 %; TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ext_clk_62mhz_n_i" TNM_NET = "ext_clk_62mhz_n_i"; NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
TIMESPEC TS_ext_clk_62mhz_n_i = PERIOD "ext_clk_62mhz_n_i" 16 ns HIGH 50 %; TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i"; NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 90536db3
...@@ -135,28 +135,27 @@ entity scb_top_synthesis is ...@@ -135,28 +135,27 @@ entity scb_top_synthesis is
ext_clk_10mhz_p_i : in std_logic; ext_clk_10mhz_p_i : in std_logic;
ext_clk_10mhz_n_i : in std_logic; ext_clk_10mhz_n_i : in std_logic;
ext_clk_62mhz_p_i : in std_logic; ljd_clk_62mhz_p_i : in std_logic;
ext_clk_62mhz_n_i : in std_logic; ljd_clk_62mhz_n_i : in std_logic;
ext_pll_status_i : in std_logic; ljd_pll_status_i : in std_logic;
ext_pll_mosi_o : out std_logic; ljd_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic; ljd_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic; ljd_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic; ljd_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic; ljd_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic; ljd_pll_reset_n_o : out std_logic;
ext_dac_main_sync_n_o : out std_logic; ljd_dac_main_sync_n_o : out std_logic;
ext_dac_main_sclk_o : out std_logic; ljd_dac_main_sclk_o : out std_logic;
ext_dac_main_data_o : out std_logic; ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_rev_id_i : in std_logic_vector (2 downto 0);
ext_board_rev_id_i : in std_logic_vector (2 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -329,10 +328,10 @@ architecture Behavioral of scb_top_synthesis is ...@@ -329,10 +328,10 @@ architecture Behavioral of scb_top_synthesis is
signal clk_ext_100 : std_logic; signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
signal ext_board_detected : std_logic := '0'; signal ljd_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic; signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic; signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic;
component scb_top_bare component scb_top_bare
generic ( generic (
...@@ -373,12 +372,18 @@ architecture Behavioral of scb_top_synthesis is ...@@ -373,12 +372,18 @@ architecture Behavioral of scb_top_synthesis is
ljd_dac_main_sync_n_o : out std_logic; ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic; ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic; ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
pll_status_i : in std_logic; pll_status_i : in std_logic;
pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
pll_miso_i : in std_logic; pll_miso_i : in std_logic;
...@@ -386,12 +391,6 @@ architecture Behavioral of scb_top_synthesis is ...@@ -386,12 +391,6 @@ architecture Behavioral of scb_top_synthesis is
pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
clk_en_o : out std_logic; clk_en_o : out std_logic;
...@@ -530,21 +529,21 @@ begin ...@@ -530,21 +529,21 @@ begin
I => fpga_clk_ref_p_i, I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i); IB => fpga_clk_ref_n_i);
U_Buf_ext_clk_62mhz : IBUFGDS U_Buf_ljd_clk_62mhz : IBUFGDS
generic map ( generic map (
DIFF_TERM => true, DIFF_TERM => true,
IOSTANDARD => "LVDS_25") IOSTANDARD => "LVDS_25")
port map ( port map (
O => ext_clk_62mhz, O => ljd_clk_62mhz,
I => ext_clk_62mhz_p_i, I => ljd_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i); IB => ljd_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR U_Buf_ljd_clk_62mhz_bufr : BUFR
port map ( port map (
CE => '1', CE => '1',
CLR => '0', CLR => '0',
I => ext_clk_62mhz, I => ljd_clk_62mhz,
O => ext_clk_62mhz_bufr); O => ljd_clk_62mhz_bufr);
U_Buf_ext_clk10mhz : IBUFDS U_Buf_ext_clk10mhz : IBUFDS
generic map ( generic map (
...@@ -571,8 +570,8 @@ begin ...@@ -571,8 +570,8 @@ begin
O => clk_10mhz, O => clk_10mhz,
I0 => clk_ext, I0 => clk_ext,
I1 => ext_clk_10MHz_bufr, I1 => ext_clk_10MHz_bufr,
S1 => ext_board_detected, S1 => ljd_detected,
S0 => NOT ext_board_detected); S0 => NOT ljd_detected);
U_Buf_CLK_DMTD : IBUFGDS U_Buf_CLK_DMTD : IBUFGDS
generic map ( generic map (
...@@ -628,7 +627,7 @@ begin ...@@ -628,7 +627,7 @@ begin
clk_ext_i => clk_ext, clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100, clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected, powerdown_i => ljd_detected,
locked_o => ext_pll_100_locked); locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m U_Ext_PLL2: ext_pll_100_to_62m
...@@ -636,12 +635,12 @@ begin ...@@ -636,12 +635,12 @@ begin
clk_ext_100_i => clk_ext_100, clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul, clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected, powerdown_i => ljd_detected,
locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul; clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz_bufr; clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse U_Extend_EXT_Reset: gc_extend_pulse
...@@ -825,15 +824,21 @@ begin ...@@ -825,15 +824,21 @@ begin
dac_main_sclk_o => dac_main_sclk_o, dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o, dac_main_data_o => dac_main_data_o,
-- Low-jitter daughterboard support -- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ext_dac_main_sync_n_o, ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ext_dac_main_sclk_o, ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
ljd_dac_main_data_o => ext_dac_main_data_o, ljd_dac_main_data_o => ljd_dac_main_data_o,
ext_board_loopback_i => ext_board_loopback_i, ljd_loopback_i => ljd_loopback_i,
ext_board_loopback_o => ext_board_loopback_o, ljd_loopback_o => ljd_loopback_o,
ext_board_clk1_en => ext_board_clk1_en, ljd_clk1_en => ljd_clk1_en,
ext_board_clk2_en => ext_board_clk2_en, ljd_clk2_en => ljd_clk2_en,
ext_board_detected_o => ext_board_detected, ljd_detected_o => ljd_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i, ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
pll_status_i => clk_10mhz, pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o, pll_mosi_o => pll_mosi_o,
...@@ -842,12 +847,6 @@ begin ...@@ -842,12 +847,6 @@ begin
pll_cs_n_o => pll_cs_n_o, pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o, pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o, pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o, clk_en_o => clk_en_o,
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 90536db3
...@@ -22,22 +22,22 @@ NET "ext_clk_10mhz_n_i" LOC = AG30; ...@@ -22,22 +22,22 @@ NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0; INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1; INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ext_clk_62mhz_p_i" LOC = AN33; NET "ljd_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34; NET "ljd_clk_62mhz_n_i" LOC = AN34;
NET "ext_board_rev_id_i[0]" LOC = AE29; NET "ljd_rev_id_i[0]" LOC = AE29;
NET "ext_board_rev_id_i[1]" LOC = AE28; NET "ljd_rev_id_i[1]" LOC = AE28;
NET "ext_board_rev_id_i[2]" LOC = AM32; NET "ljd_rev_id_i[2]" LOC = AM32;
NET "ext_board_osc_freq_i[0]" LOC = AN32; NET "ljd_osc_freq_i[0]" LOC = AN32;
NET "ext_board_osc_freq_i[1]" LOC = AP33; NET "ljd_osc_freq_i[1]" LOC = AP33;
NET "ext_board_osc_freq_i[2]" LOC = AP32; NET "ljd_osc_freq_i[2]" LOC = AP32;
NET "ext_board_clk1_en" LOC = AL31; NET "ljd_clk1_en" LOC = AL31;
NET "ext_board_clk2_en" LOC = AK31; NET "ljd_clk2_en" LOC = AK31;
NET "ext_board_loopback_i" LOC = AM31; NET "ljd_loopback_i" LOC = AM31;
NET "ext_board_loopback_o" LOC = AL30; NET "ljd_loopback_o" LOC = AL30;
#NET "dbg_clk_ext_o" LOC=AM33; #NET "dbg_clk_ext_o" LOC=AM33;
#NET "spll_dbg_o<0>" LOC=AL33; #NET "spll_dbg_o<0>" LOC=AL33;
...@@ -125,9 +125,9 @@ NET "dac_main_sync_n_o" LOC="AM17"; ...@@ -125,9 +125,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17"; NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17"; NET "dac_main_data_o" LOC="AP17";
NET "ext_dac_main_sync_n_o" LOC = AH32; NET "ljd_dac_main_sync_n_o" LOC = AH32;
NET "ext_dac_main_sclk_o" LOC = AK32; NET "ljd_dac_main_sclk_o" LOC = AK32;
NET "ext_dac_main_data_o" LOC = AK33; NET "ljd_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18"; NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16"; NET "pll_sck_o" LOC="AE16";
...@@ -137,13 +137,13 @@ NET "pll_reset_n_o" LOC="AL16"; ...@@ -137,13 +137,13 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13"; NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18"; NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27; NET "ljd_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26; NET "ljd_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27; NET "ljd_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28; NET "ljd_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29; NET "ljd_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25; NET "ljd_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34; NET "ljd_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11"; NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11"; NET "uart_rxd_i" LOC="D11";
...@@ -305,10 +305,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%; ...@@ -305,10 +305,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i; NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%; TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ext_clk_62mhz_p_i" TNM_NET = "ext_clk_62mhz_p_i"; NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
TIMESPEC TS_ext_clk_62mhz_p_i = PERIOD "ext_clk_62mhz_p_i" 16 ns HIGH 50 %; TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ext_clk_62mhz_n_i" TNM_NET = "ext_clk_62mhz_n_i"; NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
TIMESPEC TS_ext_clk_62mhz_n_i = PERIOD "ext_clk_62mhz_n_i" 16 ns HIGH 50 %; TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i"; NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 90536db3
...@@ -130,27 +130,27 @@ entity scb_top_synthesis is ...@@ -130,27 +130,27 @@ entity scb_top_synthesis is
-- WRS Low Jitter board -- WRS Low Jitter board
ext_clk_10mhz_p_i : in std_logic; ext_clk_10mhz_p_i : in std_logic;
ext_clk_10mhz_n_i : in std_logic; ext_clk_10mhz_n_i : in std_logic;
ext_clk_62mhz_p_i : in std_logic; ljd_clk_62mhz_p_i : in std_logic;
ext_clk_62mhz_n_i : in std_logic; ljd_clk_62mhz_n_i : in std_logic;
ext_pll_status_i : in std_logic; ljd_pll_status_i : in std_logic;
ext_pll_mosi_o : out std_logic; ljd_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic; ljd_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic; ljd_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic; ljd_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic; ljd_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic; ljd_pll_reset_n_o : out std_logic;
ext_dac_main_sync_n_o : out std_logic; ljd_dac_main_sync_n_o : out std_logic;
ext_dac_main_sclk_o : out std_logic; ljd_dac_main_sclk_o : out std_logic;
ext_dac_main_data_o : out std_logic; ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_rev_id_i : in std_logic_vector (2 downto 0); ljd_rev_id_i : in std_logic_vector (2 downto 0);
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
...@@ -329,9 +329,9 @@ architecture Behavioral of scb_top_synthesis is ...@@ -329,9 +329,9 @@ architecture Behavioral of scb_top_synthesis is
signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
signal ext_board_detected : std_logic := '0'; signal ljd_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic; signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic; signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic;
component scb_top_bare component scb_top_bare
generic ( generic (
...@@ -372,12 +372,18 @@ architecture Behavioral of scb_top_synthesis is ...@@ -372,12 +372,18 @@ architecture Behavioral of scb_top_synthesis is
ljd_dac_main_sync_n_o : out std_logic; ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic; ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic; ljd_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic; ljd_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic; ljd_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic; ljd_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic; ljd_clk2_en : out std_logic;
ext_board_detected_o : out std_logic; ljd_detected_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
ljd_pll_sck_o : out std_logic;
ljd_pll_cs_n_o : out std_logic;
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
pll_status_i : in std_logic; pll_status_i : in std_logic;
pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
pll_miso_i : in std_logic; pll_miso_i : in std_logic;
...@@ -385,12 +391,6 @@ architecture Behavioral of scb_top_synthesis is ...@@ -385,12 +391,6 @@ architecture Behavioral of scb_top_synthesis is
pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
clk_en_o : out std_logic; clk_en_o : out std_logic;
...@@ -529,21 +529,21 @@ begin ...@@ -529,21 +529,21 @@ begin
I => fpga_clk_ref_p_i, I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i); IB => fpga_clk_ref_n_i);
U_Buf_ext_clk_62mhz : IBUFGDS U_Buf_ljd_clk_62mhz : IBUFGDS
generic map ( generic map (
DIFF_TERM => true, DIFF_TERM => true,
IOSTANDARD => "LVDS_25") IOSTANDARD => "LVDS_25")
port map ( port map (
O => ext_clk_62mhz, O => ljd_clk_62mhz,
I => ext_clk_62mhz_p_i, I => ljd_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i); IB => ljd_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR U_Buf_ljd_clk_62mhz_bufr : BUFR
port map ( port map (
CE => '1', CE => '1',
CLR => '0', CLR => '0',
I => ext_clk_62mhz, I => ljd_clk_62mhz,
O => ext_clk_62mhz_bufr); O => ljd_clk_62mhz_bufr);
U_Buf_ext_clk10mhz : IBUFDS U_Buf_ext_clk10mhz : IBUFDS
generic map ( generic map (
...@@ -570,8 +570,8 @@ begin ...@@ -570,8 +570,8 @@ begin
O => clk_10mhz, O => clk_10mhz,
I0 => clk_ext, I0 => clk_ext,
I1 => ext_clk_10MHz_bufr, I1 => ext_clk_10MHz_bufr,
S1 => ext_board_detected, S1 => ljd_detected,
S0 => NOT ext_board_detected S0 => NOT ljd_detected
); );
U_Buf_CLK_DMTD : IBUFGDS U_Buf_CLK_DMTD : IBUFGDS
...@@ -628,7 +628,7 @@ begin ...@@ -628,7 +628,7 @@ begin
clk_ext_i => clk_ext, clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100, clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected, powerdown_i => ljd_detected,
locked_o => ext_pll_100_locked); locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m U_Ext_PLL2: ext_pll_100_to_62m
...@@ -636,12 +636,12 @@ begin ...@@ -636,12 +636,12 @@ begin
clk_ext_100_i => clk_ext_100, clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul, clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected, powerdown_i => ljd_detected,
locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul; clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz_bufr; clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
--dbg_clk_ext_o <= clk_ext_mul; --dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
...@@ -828,15 +828,21 @@ begin ...@@ -828,15 +828,21 @@ begin
dac_main_sclk_o => dac_main_sclk_o, dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o, dac_main_data_o => dac_main_data_o,
-- Low-jitter daughterboard support -- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ext_dac_main_sync_n_o, ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ext_dac_main_sclk_o, ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
ljd_dac_main_data_o => ext_dac_main_data_o, ljd_dac_main_data_o => ljd_dac_main_data_o,
ext_board_loopback_i => ext_board_loopback_i, ljd_loopback_i => ljd_loopback_i,
ext_board_loopback_o => ext_board_loopback_o, ljd_loopback_o => ljd_loopback_o,
ext_board_clk1_en => ext_board_clk1_en, ljd_clk1_en => ljd_clk1_en,
ext_board_clk2_en => ext_board_clk2_en, ljd_clk2_en => ljd_clk2_en,
ext_board_detected_o => ext_board_detected, ljd_detected_o => ljd_detected,
ext_board_osc_freq_i => ext_board_osc_freq_i, ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
ljd_pll_sck_o => ljd_pll_sck_o,
ljd_pll_cs_n_o => ljd_pll_cs_n_o,
ljd_pll_sync_n_o => ljd_pll_sync_n_o,
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
pll_status_i => clk_10mhz, pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o, pll_mosi_o => pll_mosi_o,
...@@ -845,12 +851,6 @@ begin ...@@ -845,12 +851,6 @@ begin
pll_cs_n_o => pll_cs_n_o, pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o, pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o, pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o, clk_en_o => clk_en_o,
......
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