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White Rabbit Switch - Gateware
Commit 93a74f10 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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top/bare_top: move DDMTD samplers to the PHY module, g_without_network… 

top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore
parent 6b3c0e71
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Showing with 25 additions and 6 deletions
top/bare_top/scb_top_bare.vhd
View file @ 93a74f10
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk -- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-02-21 -- Created : 2012-02-21
-- Last update: 2014-03-17 -- Last update: 2018-06-16
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -282,7 +282,7 @@ architecture rtl of scb_top_bare is ...@@ -282,7 +282,7 @@ architecture rtl of scb_top_bare is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal clk_sys : std_logic; signal clk_sys : std_logic;
signal clk_rx_vec : std_logic_vector(c_NUM_PORTS-1 downto 0); signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(c_NUM_PORTS-1 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -603,12 +603,14 @@ begin ...@@ -603,12 +603,14 @@ begin
generic map ( generic map (
g_num_rx_clocks => c_NUM_PORTS, g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2, g_num_ext_clks => 2,
g_simulation => g_simulation) g_simulation => g_simulation,
g_use_sampled_rx_clocks => true)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec, clk_rx_i => clk_rx_vec,
clk_rx_sampled_i => clk_rx_sampled_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i, clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i, clk_ext_mul_locked_i => clk_ext_mul_locked_i,
...@@ -798,6 +800,8 @@ begin ...@@ -798,6 +800,8 @@ begin
phy_rst_o => phys_o(i).rst, phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen, phy_loopen_o => phys_o(i).loopen,
phy_debug_i => phys_i(i).debug,
phy_debug_o => phys_o(i).debug,
phy_rdy_i => phys_i(i).rdy, phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk, phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, -- phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
...@@ -877,6 +881,7 @@ begin ...@@ -877,6 +881,7 @@ begin
--------------------------- ---------------------------
clk_rx_vec(i) <= phys_i(i).rx_clk; clk_rx_vec(i) <= phys_i(i).rx_clk;
clk_rx_sampled_vec(i) <= phys_i(i).rx_sampled_clk;
end generate gen_endpoints_and_phys; end generate gen_endpoints_and_phys;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 93a74f10
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk -- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-02-21 -- Created : 2012-02-21
-- Last update: 2014-02-14 -- Last update: 2018-02-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -51,6 +51,8 @@ package wrsw_top_pkg is ...@@ -51,6 +51,8 @@ package wrsw_top_pkg is
syncen : std_logic; syncen : std_logic;
tx_data : std_logic_vector(15 downto 0); tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0); tx_k : std_logic_vector(1 downto 0);
debug : std_logic_vector(15 downto 0);
end record; end record;
type t_phyif_input is record type t_phyif_input is record
...@@ -59,10 +61,12 @@ package wrsw_top_pkg is ...@@ -59,10 +61,12 @@ package wrsw_top_pkg is
tx_enc_err : std_logic; tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0); rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic; rx_clk : std_logic;
rx_sampled_clk : std_logic;
rx_k : std_logic_vector(1 downto 0); rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic; rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0); rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic; rdy : std_logic;
debug : std_logic_vector(15 downto 0);
end record; end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output; type t_phyif_output_array is array(integer range <>) of t_phyif_output;
...@@ -123,22 +127,30 @@ package wrsw_top_pkg is ...@@ -123,22 +127,30 @@ package wrsw_top_pkg is
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_gtx_i : in std_logic; clk_gtx_i : in std_logic;
clk_dmtd_i : in std_logic;
tx_data_i : in std_logic_vector(15 downto 0); tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0); tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic; tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic; tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic; rx_rbclk_o : out std_logic;
rx_rbclk_sampled_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0); rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0); rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic; rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0); rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic; rst_i : in std_logic;
loopen_i : in std_logic; loopen_i : in std_logic;
debug_i : in std_logic_vector(15 downto 0);
debug_o : out std_logic_vector(15 downto 0);
pad_txn_o : out std_logic; pad_txn_o : out std_logic;
pad_txp_o : out std_logic; pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0'; pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0'; pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic); rdy_o : out std_logic;
tx_sampled_i : in std_logic := '0';
rx_sampled_i : in std_logic := '0'
);
end component; end component;
component xwr_pps_gen component xwr_pps_gen
...@@ -208,12 +220,14 @@ package wrsw_top_pkg is ...@@ -208,12 +220,14 @@ package wrsw_top_pkg is
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer; g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean;
g_use_sampled_rx_clocks : boolean);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0); clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
......
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