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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
98089675
Commit
98089675
authored
Dec 20, 2016
by
Mattia Rizzi
Committed by
Grzegorz Daniluk
Aug 09, 2019
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Added module to check the presence of the external board
parent
31787035
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Manifest.py
modules/wrsw_ext_board/Manifest.py
+2
-0
ext_board_check.vhd
modules/wrsw_ext_board/ext_board_check.vhd
+127
-0
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modules/wrsw_ext_board/Manifest.py
0 → 100644
View file @
98089675
files
=
[
"ext_board_check.vhd"
];
modules/wrsw_ext_board/ext_board_check.vhd
0 → 100644
View file @
98089675
-------------------------------------------------------------------------------
-- Title : ext_board_check
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : ext_board_check.vhd
-- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- FSM to check the presence of the WRS Low jitter daughterboard
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2016 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wrsw_top_pkg
.
all
;
library
UNISIM
;
use
UNISIM
.
vcomponents
.
all
;
entity
ext_board_check
is
generic
(
g_pattern
:
std_logic_vector
(
63
downto
0
)
:
=
x"CAFED00DCAFED00D"
;
g_clk_divider
:
integer
:
=
16
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
loopback_i
:
in
std_logic
;
loopback_o
:
out
std_logic
;
board_detected_o
:
out
std_logic
);
end
ext_board_check
;
architecture
Behavioral
of
ext_board_check
is
signal
clk_divider
:
integer
range
0
to
g_clk_divider
-1
;
signal
clk_en
:
std_logic
;
signal
bit_position
:
integer
range
0
to
g_pattern
'length
-1
;
type
fsm_states
is
(
init
,
write_bit
,
read_bit
,
done
);
signal
fsm_state
:
fsm_states
:
=
init
;
signal
error_detected
:
std_logic
;
begin
clock_divider_inst
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
clk_divider
<=
clk_divider
+
1
;
if
(
clk_divider
=
g_clk_divider
-
1
)
then
clk_divider
<=
0
;
clk_en
<=
'1'
;
else
clk_en
<=
'0'
;
end
if
;
end
if
;
end
process
;
FSM_INST
:
process
(
clk_sys_i
)
begin
if
rst_n_i
=
'0'
then
board_detected_o
<=
'0'
;
fsm_state
<=
init
;
elsif
rising_edge
(
clk_sys_i
)
then
case
fsm_state
is
when
init
=>
board_detected_o
<=
'0'
;
bit_position
<=
0
;
fsm_state
<=
write_bit
;
error_detected
<=
'0'
;
when
write_bit
=>
loopback_o
<=
g_pattern
(
bit_position
);
if
(
clk_en
=
'1'
)
then
fsm_state
<=
read_bit
;
end
if
;
when
read_bit
=>
if
(
g_pattern
(
bit_position
)
=
loopback_i
)
then
if
(
bit_position
=
g_pattern
'length
-1
)
then
fsm_state
<=
done
;
else
bit_position
<=
bit_position
+
1
;
fsm_state
<=
write_bit
;
end
if
;
else
error_detected
<=
'1'
;
fsm_state
<=
done
;
end
if
;
when
done
=>
board_detected_o
<=
not
error_detected
;
when
others
=>
fsm_state
<=
init
;
end
case
;
end
if
;
end
process
;
end
Behavioral
;
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