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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
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a5a71704
Commit
a5a71704
authored
Jul 13, 2015
by
Grzegorz Daniluk
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scb_18ports: relaxing dmtd clock maxskew constraint
parent
71988a77
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scb_top_synthesis.vhd
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top/scb_18ports/scb_top_synthesis.vhd
View file @
a5a71704
...
...
@@ -234,7 +234,7 @@ architecture Behavioral of scb_top_synthesis is
signal
pllout_clk_fb
:
std_logic
;
attribute
maxskew
:
string
;
attribute
maxskew
of
clk_dmtd
:
signal
is
"
0.5
ns"
;
attribute
maxskew
of
clk_dmtd
:
signal
is
"
1.0
ns"
;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
...
...
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