scb_18ports: relaxing dmtd clock maxskew constraint

a5a71704 · Grzegorz Daniluk · 71988a77 · a5a71704
Commit a5a71704 authored Jul 13, 2015 by Grzegorz Daniluk
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scb_top_synthesis.vhd top/scb_18ports/scb_top_synthesis.vhd +1 -1

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--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -234,7 +234,7 @@ architecture Behavioral of scb_top_synthesis is
  signal pllout_clk_fb                          : std_logic;
  attribute maxskew: string;
-  attribute maxskew of clk_dmtd : signal is "0.5ns";
+  attribute maxskew of clk_dmtd : signal is "1.0ns";
  -----------------------------------------------------------------------------
  -- Component declarations
  -----------------------------------------------------------------------------