sim: updated wbgen2 reg definitions

a7384a41 · Tomasz Wlostowski · 15b390a7 · a7384a41 · a7384a41
Commit a7384a41 authored Jun 22, 2012 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 23 additions and 11 deletions

softpll_regs_ng.vh sim/softpll_regs_ng.vh +19 -10

txtsu_regs.v sim/txtsu_regs.v +4 -1

No files found.
--- a/sim/softpll_regs_ng.vh
+++ b/sim/softpll_regs_ng.vh
@@ -7,32 +7,41 @@
 `define SPLL_CSR_N_OUT 32'h00070000
 `define SPLL_CSR_PER_EN_OFFSET 19
 `define SPLL_CSR_PER_EN 32'h00080000
-`define ADDR_SPLL_DCCR                 7'h4
+`define ADDR_SPLL_ECCR                 7'h4
+`define SPLL_ECCR_EXT_EN_OFFSET 0
+`define SPLL_ECCR_EXT_EN 32'h00000001
+`define SPLL_ECCR_EXT_SUPPORTED_OFFSET 1
+`define SPLL_ECCR_EXT_SUPPORTED 32'h00000002
+`define SPLL_ECCR_ALIGN_EN_OFFSET 2
+`define SPLL_ECCR_ALIGN_EN 32'h00000004
+`define SPLL_ECCR_ALIGN_DONE_OFFSET 3
+`define SPLL_ECCR_ALIGN_DONE 32'h00000008
+`define ADDR_SPLL_DCCR                 7'h8
 `define SPLL_DCCR_GATE_DIV_OFFSET 0
 `define SPLL_DCCR_GATE_DIV 32'h0000003f
-`define ADDR_SPLL_RCGER                7'h8
+`define ADDR_SPLL_RCGER                7'hc
 `define SPLL_RCGER_GATE_SEL_OFFSET 0
 `define SPLL_RCGER_GATE_SEL 32'hffffffff
-`define ADDR_SPLL_OCCR                 7'hc
+`define ADDR_SPLL_OCCR                 7'h10
 `define SPLL_OCCR_OUT_EN_OFFSET 0
 `define SPLL_OCCR_OUT_EN 32'h000000ff
 `define SPLL_OCCR_OUT_LOCK_OFFSET 8
 `define SPLL_OCCR_OUT_LOCK 32'h0000ff00
-`define ADDR_SPLL_RCER                 7'h10
-`define ADDR_SPLL_OCER                 7'h14
-`define ADDR_SPLL_PER_HPLL             7'h18
+`define ADDR_SPLL_RCER                 7'h14
+`define ADDR_SPLL_OCER                 7'h18
+`define ADDR_SPLL_PER_HPLL             7'h1c
 `define SPLL_PER_HPLL_ERROR_OFFSET 0
 `define SPLL_PER_HPLL_ERROR 32'h0000ffff
 `define SPLL_PER_HPLL_VALID_OFFSET 16
 `define SPLL_PER_HPLL_VALID 32'h00010000
-`define ADDR_SPLL_DAC_HPLL             7'h1c
-`define ADDR_SPLL_DAC_MAIN             7'h20
+`define ADDR_SPLL_DAC_HPLL             7'h20
+`define ADDR_SPLL_DAC_MAIN             7'h24
 `define SPLL_DAC_MAIN_VALUE_OFFSET 0
 `define SPLL_DAC_MAIN_VALUE 32'h0000ffff
 `define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
 `define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
-`define ADDR_SPLL_DEGLITCH_THR         7'h24
-`define ADDR_SPLL_DFR_SPLL             7'h28
+`define ADDR_SPLL_DEGLITCH_THR         7'h28
+`define ADDR_SPLL_DFR_SPLL             7'h2c
 `define SPLL_DFR_SPLL_VALUE_OFFSET 0
 `define SPLL_DFR_SPLL_VALUE 32'h7fffffff
 `define SPLL_DFR_SPLL_EOS_OFFSET 31

--- a/sim/txtsu_regs.v
+++ b/sim/txtsu_regs.v
@@ -20,7 +20,10 @@
 `define TXTSU_TSF_R1_PID 32'h0000001f
 `define TXTSU_TSF_R1_FID_OFFSET 16
 `define TXTSU_TSF_R1_FID 32'hffff0000
-`define ADDR_TXTSU_TSF_CSR             5'h18
+`define ADDR_TXTSU_TSF_R2              5'h18
+`define TXTSU_TSF_R2_INCORRECT_OFFSET 0
+`define TXTSU_TSF_R2_INCORRECT 32'h00000001
+`define ADDR_TXTSU_TSF_CSR             5'h1c
 `define TXTSU_TSF_CSR_FULL_OFFSET 16
 `define TXTSU_TSF_CSR_FULL 32'h00010000
 `define TXTSU_TSF_CSR_EMPTY_OFFSET 17