HWIU can replace HWDU

HWIU provides more information about the gateware build and in the same time can read debug registers and drive chipscope mux in the same way HWDU does it. For now one of them can be selected with generic, but once I test HWIU I'll remove HWDU module.

HWIU can replace HWDU
HWIU provides more information about the gateware build and in the same time can read debug registers and drive chipscope mux in the same way HWDU does it. For now one of them can be selected with generic, but once I test HWIU I'll remove HWDU module.
d13866aa · Grzegorz Daniluk · cae6f09f · d13866aa · d13866aa · d13866aa
Commit d13866aa authored Feb 05, 2014 by Grzegorz Daniluk
5 changed files
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -27,6 +27,7 @@ entity scb_top_bare is
    g_with_TRU        : boolean := false;
    g_with_TATSU      : boolean := false;
    g_with_HWDU       : boolean := false;
+    g_with_HWIU       : boolean := false;
    g_with_PSTATS     : boolean := true
    );
  port (
@@ -965,9 +966,28 @@ begin
                ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
  end generate gen_events_assemble;

-  --=====================================--
-  --               HWDU                  --
-  --=====================================--
+  --============================================================--
+  -- Hardware Info Unit providing firmware version for software --
+  --============================================================--
+
+  gen_HWIU: if(g_with_HWIU = true) generate
+    U_HWIU: xwrsw_hwiu
+      generic map(
+        g_interface_mode => PIPELINED,
+        g_address_granularity => BYTE,
+        g_ndbg_regs => c_DBG_N_REGS,
+        g_ver_major => 3,
+        g_ver_minor => 3,
+        g_build     => 1)
+      port map(
+        rst_n_i       => rst_n_periph,
+        clk_i         => clk_sys,
+        dbg_regs_i    => dbg_n_regs,
+        dbg_chps_id_o => dbg_chps_id,
+        wb_i          => cnx_master_out(c_SLAVE_HWDU),
+        wb_o          => cnx_master_in(c_SLAVE_HWDU));
+  end generate;
+
  gen_HWDU: if(g_with_HWDU = true) generate
    U_HWDU : xwrsw_hwdu
      generic map(
@@ -986,7 +1006,8 @@ begin
        dbg_n_regs(  32-1 downto 0)                 <= c_GW_VERSION;
 --         dbg_n_regs(2*32-1 downto c_DBG_V_SWCORE+32) <= (others=>'0');
    end generate;
-    gen_no_HWDU: if(g_with_HWDU = false) generate
+
+    gen_no_HWDU: if(g_with_HWDU = false and g_with_HWIU = false) generate
      cnx_master_in(c_SLAVE_HWDU).ack   <= '1';
      cnx_master_in(c_SLAVE_HWDU).dat   <= c_GW_VERSION;--x"deadbeef";
      cnx_master_in(c_SLAVE_HWDU).err   <= '0';
@@ -1060,21 +1081,6 @@ begin
  clk_dmtd_divsel_o <= '1';             -- choose 62.5 MHz DDMTD clock
  clk_sys_o         <= clk_sys;

-  -----------------------------------------------------------------------------
-  -- Hardware Info Unit providing firmware version for software
-  -----------------------------------------------------------------------------
--  U_HWIU: xwrsw_hwiu
--    generic map(
--      g_interface_mode => PIPELINED,
--      g_address_granularity => BYTE,
--      g_ver_major => 3,
--      g_ver_minor => 3,
--      g_build     => 1)
--    port map(
--      rst_n_i => rst_n_periph,
--      clk_i   => clk_sys,
--      wb_i    => cnx_master_out(c_SLAVE_HWIU),
--      wb_o    => cnx_master_in(c_SLAVE_HWIU));

 --   
 --  CS_ICON : chipscope_icon

--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
@@ -140,7 +140,8 @@ begin  -- rtl
      g_without_network => false,
      g_with_TRU        => true,
      g_with_TATSU      => true,
-      g_with_HWDU       => true)
+      g_with_HWDU       => true,
+      g_with_HWIU       => false)
    port map (
      sys_rst_n_i         => sys_rst_n_i,
      clk_startup_i       => clk_startup_i,

--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
@@ -357,7 +357,8 @@ package wrsw_components_pkg is
      rst_n_i : in std_logic;
      clk_i   : in std_logic;
  
-      dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others=>'0');
+      dbg_regs_i    : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others=>'0');
+      dbg_chps_id_o : out std_logic_vector(7 downto 0);
  
      wb_i : in  t_wishbone_slave_in;
      wb_o : out t_wishbone_slave_out);

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -224,7 +224,8 @@ package wrsw_top_pkg is
      g_without_network : boolean;
      g_with_TRU        : boolean  := false;
      g_with_TATSU      : boolean  := false;
-      g_with_HWDU       : boolean  := false);
+      g_with_HWDU       : boolean  := false;
+      g_with_HWIU       : boolean  := false);
    port (
      sys_rst_n_i         : in  std_logic;
      clk_startup_i       : in  std_logic;
@@ -406,7 +407,6 @@ package wrsw_top_pkg is
      wb_o : out t_wishbone_slave_out);
  end component;

-
  --TEMP
  component dummy_rmon
    generic(

--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -239,7 +239,8 @@ architecture Behavioral of scb_top_synthesis is
      g_without_network : boolean;
      g_with_TRU        : boolean;
      g_with_TATSU      : boolean;
-      g_with_HWDU       : boolean);
+      g_with_HWDU       : boolean;
+      g_with_HWIU       : boolean);
    port (
      sys_rst_n_i         : in  std_logic;
      clk_startup_i       : in  std_logic;
@@ -597,7 +598,8 @@ begin
      g_without_network => false,
      g_with_TRU        => true,
      g_with_TATSU      => true,
-      g_with_HWDU       => true)
+      g_with_HWDU       => false,
+      g_with_HWIU       => true)
    port map (
      sys_rst_n_i         => sys_rst_n_i,
      clk_startup_i       => clk_sys_startup,