Commit d23cfc82 authored by Maciej Lipinski's avatar Maciej Lipinski

swcore[new mpm]: removing old generics

parent d89af41c
......@@ -69,17 +69,7 @@ entity swc_core is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
g_mpm_fetch_next_pg_in_advance : boolean ;
-- probably useless with new memory
g_ctrl_width : integer ; --:= c_swc_ctrl_width
-- g_data_width : integer ;--:= c_swc_data_width
-- g_mem_size : integer ;--:= c_swc_packet_mem_size
-- g_page_size : integer ;--:= c_swc_page_size
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
g_mpm_fetch_next_pg_in_advance : boolean
);
port (
clk_i : in std_logic;
......@@ -157,12 +147,7 @@ architecture rtl of swc_core is
g_mpm_page_size => g_mpm_page_size,
g_mpm_ratio => g_mpm_ratio,
g_mpm_fifo_size => g_mpm_fifo_size,
g_mpm_fetch_next_pg_in_advance => g_mpm_fetch_next_pg_in_advance,
g_ctrl_width => g_ctrl_width,
g_packet_mem_multiply => g_packet_mem_multiply,
g_input_block_fifo_size => g_input_block_fifo_size,
g_input_block_fifo_full_in_advance => g_input_block_fifo_full_in_advance
g_mpm_fetch_next_pg_in_advance => g_mpm_fetch_next_pg_in_advance
)
port map(
clk_i => clk_i,
......
......@@ -160,77 +160,6 @@ package swc_swcore_pkg is
);
end component;
component xswc_input_block_old is
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_prio_width : integer ;--:= c_swc_prio_width;
g_max_pck_size_width : integer ;--:= c_swc_max_pck_size_width
g_usecount_width : integer ;--:= c_swc_usecount_width
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_input_block_cannot_accept_data : string := "drop_pck"; --"stall_o", "rty_o" -- Don't CHANGE !
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- pWB : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-------------------------------------------------------------------------------
-- I/F with Page allocator (MMU)
-------------------------------------------------------------------------------
mmu_page_alloc_req_o : out std_logic;
mmu_page_alloc_done_i : in std_logic;
mmu_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
mmu_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_addr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
mmu_set_usecnt_o : out std_logic;
mmu_set_usecnt_done_i : in std_logic;
mmu_usecnt_o : out std_logic_vector(g_usecount_width - 1 downto 0);
mmu_nomem_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
rtu_drop_i : in std_logic;
rtu_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Multiport Memory (MPU)
-------------------------------------------------------------------------------
mpm_pckstart_o : out std_logic;
mpm_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
mpm_pagereq_o : out std_logic;
mpm_pageend_i : in std_logic;
mpm_data_o : out std_logic_vector(g_data_width - 1 downto 0);
mpm_ctrl_o : out std_logic_vector(g_ctrl_width - 1 downto 0);
mpm_drdy_o : out std_logic;
mpm_full_i : in std_logic;
mpm_flush_o : out std_logic;
mpm_wr_sync_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Page Transfer Arbiter (PTA)
-------------------------------------------------------------------------------
pta_transfer_pck_o : out std_logic;
pta_transfer_ack_i : in std_logic;
pta_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
pta_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0)
);
end component;
component xswc_input_block is
generic (
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
......@@ -244,12 +173,7 @@ package swc_swcore_pkg is
g_mpm_data_width : integer ; -- it needs to be wb_data_width + wb_addr_width
g_page_size : integer ;
g_partial_select_width : integer ;
g_ll_data_width : integer ;
-- probably useless with new memory
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance
g_ll_data_width : integer
);
port (
clk_i : in std_logic;
......@@ -556,13 +480,7 @@ component swc_multiport_pck_pg_free_module is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
g_mpm_fetch_next_pg_in_advance : boolean ;
-- probably useless with new memory
g_ctrl_width : integer ; --:= c_swc_ctrl_width
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
g_mpm_fetch_next_pg_in_advance : boolean
);
port (
clk_i : in std_logic;
......
......@@ -56,7 +56,7 @@ use work.mpm_pkg.all;
entity xswc_core is
generic(
g_prio_num : integer ;--:= c_swc_output_prio_num;
g_prio_num : integer ;--:= c_swc_output_prio_num; [works only for value of 8, output_block-causes problem]
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_num_ports : integer ;--:= c_swc_num_ports
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
......@@ -72,18 +72,7 @@ entity xswc_core is
g_mpm_page_size : integer ;
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
g_mpm_fetch_next_pg_in_advance : boolean ;
-- probably useless with new memory
g_ctrl_width : integer ; --:= c_swc_ctrl_width
-- g_data_width : integer ;--:= c_swc_data_width
-- g_mem_size : integer ;--:= c_swc_packet_mem_size
-- g_page_size : integer ;--:= c_swc_page_size
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
g_mpm_fetch_next_pg_in_advance : boolean
);
port (
clk_i : in std_logic;
......@@ -291,11 +280,7 @@ architecture rtl of xswc_core is
g_mpm_data_width => c_mpm_data_width,
g_page_size => g_mpm_page_size,
g_partial_select_width => c_mpm_partial_sel_width,
g_ll_data_width => c_ll_data_width,
g_ctrl_width => g_ctrl_width,
g_packet_mem_multiply => g_packet_mem_multiply,
g_input_block_fifo_size => g_input_block_fifo_size,
g_input_block_fifo_full_in_advance => g_input_block_fifo_full_in_advance
g_ll_data_width => c_ll_data_width
)
port map (
clk_i => clk_i,
......
......@@ -109,12 +109,7 @@ entity xswc_input_block is
g_mpm_data_width : integer ; -- it needs to be wb_data_width + wb_addr_width
g_page_size : integer ;
g_partial_select_width : integer ;
g_ll_data_width : integer ;
-- probably useless with new memory
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance
g_ll_data_width : integer
);
port (
clk_i : in std_logic;
......@@ -232,7 +227,7 @@ end xswc_input_block;
architecture syn of xswc_input_block is
constant c_input_fifo_size_log2 : integer := integer(CEIL(LOG2(real(g_input_block_fifo_size - 1))));
-- constant c_input_fifo_size_log2 : integer := integer(CEIL(LOG2(real(g_input_block_fifo_size - 1))));
constant c_page_size_width : integer := integer(CEIL(LOG2(real(g_page_size + 1))));
type t_page_alloc is(S_IDLE, -- waiting for some work :)
......
......@@ -267,11 +267,7 @@ U_xswc_core: xswc_core
g_mpm_page_size => 64,
g_mpm_ratio => 2,
g_mpm_fifo_size => 4,
g_mpm_fetch_next_pg_in_advance => false,
g_ctrl_width => 4,
g_packet_mem_multiply => 16,
g_input_block_fifo_size => (2 * 16),
g_input_block_fifo_full_in_advance => ((2 * 16) - 3)
g_mpm_fetch_next_pg_in_advance => false
)
port map(
clk_i => clk_i,
......
......@@ -73,12 +73,7 @@ module swc_core_wrapper_generic
.g_mpm_page_size (`c_mpm_page_size),
.g_mpm_ratio (`c_mpm_ratio),
.g_mpm_fifo_size (`c_mpm_fifo_size),
.g_mpm_fetch_next_pg_in_advance (`c_mpm_fetch_next_pg_in_advance),
.g_ctrl_width (`c_ctrl_width),
.g_packet_mem_multiply (`c_packet_mem_multiply),
.g_input_block_fifo_size (`c_input_block_fifo_size),
.g_input_block_fifo_full_in_advance (`c_input_block_fifo_full_in_advance)
.g_mpm_fetch_next_pg_in_advance (`c_mpm_fetch_next_pg_in_advance)
) DUT_swc_core(
.clk_i (clk_i),
.clk_mpm_core_i (clk_mpm_core_i),
......
......@@ -24,7 +24,7 @@
`define c_num_ports 16 //MAX: 16 //
////////////////////////////////////////////////////////////////
`define c_prio_num 8 // c_swc_output_prio_num,
`define c_prio_num 8 // c_swc_output_prio_num, [does not work, output block]
`define c_max_pck_size 10 * 1024 // 10kB -- c_swc_max_pck_size,
`define c_mpm_mem_size 65536 //c_swc_packet_mem_size,
......@@ -43,12 +43,6 @@
`define c_input_block_cannot_accept_data "drop_pck" //"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
`define c_output_block_per_prio_fifo_size 64 //c_swc_output_fifo_size,
`define c_ctrl_width 4 //c_swc_ctrl_width,
`define c_packet_mem_multiply 16 //c_swc_packet_mem_multiply,
`define c_input_block_fifo_size (2 * 16) //c_swc_input_fifo_size,
`define c_input_block_fifo_full_in_advance ((2 * 16) - 3) // c_swc_fifo_full_in_advance
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment