CI: update YML file

- Add execution of script to generate files with repo versions - Commented out 8p synthesize, uncommeted 18p synthesis - started playing with conditional sythesis (commented out)

CI: update YML file
- Add execution of script to generate files with repo versions - Commented out 8p synthesize, uncommeted 18p synthesis - started playing with conditional sythesis (commented out)
d9b3cc2a · Maciej Lipinski · 5187d38a · d9b3cc2a
Commit d9b3cc2a authored Nov 30, 2023 by Maciej Lipinski
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.gitlab-ci.yml .gitlab-ci.yml +59 -46

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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -16,6 +16,8 @@ stages:
 #     - apt-get install -y python
 #     - cd top/bare_top
 #     - python gen_sdbsyn.py --project wr_switch
+#     - cd ../../modules/wrsw_hwiu
+#     - python gen_ver.py
 #     - cd ../../
 #     - cd sim
 #     - ln -s ../ip_cores/wr-cores/sim wr-hdl
@@ -25,50 +27,61 @@ stages:
 #     - make
 #     - vsim -c -do run.do

-job_scb_top_8p_syn:
-    stage: syn
-    tags:
-     - xilinx_ISE_14.7 
-    script:
-     - /entrypoint.sh
-     - source ~/setup_ise147.sh
-     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-     - cd top/bare_top
-     - python gen_sdbsyn.py --project wr_switch
-     - cat synthesis_descriptor.vhd
-     - cd ../../syn/scb_8ports 
-     - hdlmake makefile 
-     - make
-    artifacts:
-     name: SCB_TOP_8P_CI_$CI_JOB_ID
-     paths:
-     - syn/scb_8ports/*.syr
-     - syn/scb_8ports/*.mrp
-     - syn/scb_8ports/*.bit
-     - syn/scb_8ports/*.bin
-     - syn/scb_8ports/*.par
-     - syn/scb_8ports/*.twr
+#job_scb_top_8p_syn:
+   #stage: syn
+   #tags:
+    #- xilinx_ISE_14.7 
+   #script:
+    #- /entrypoint.sh
+    #- source ~/setup_ise147.sh
+    #- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    #- cd top/bare_top
+    #- python gen_sdbsyn.py --project wr_switch
+    #- cat synthesis_descriptor.vhd
+    #- cd ../../modules/wrsw_hwiu
+    #- python gen_ver.py
+    #- cat gw_ver_pkg.vhd
+    #- cd ../../syn/scb_8ports 
+    #- hdlmake makefile 
+    #- make
+   #artifacts:
+    #name: SCB_TOP_8P_CI_$CI_JOB_ID
+    #paths:
+    #- syn/scb_8ports/*.syr
+    #- syn/scb_8ports/*.mrp
+    #- syn/scb_8ports/*.bit
+    #- syn/scb_8ports/*.bin
+    #- syn/scb_8ports/*.par
+    #- syn/scb_8ports/*.twr

-#job_scb_top_18p_syn:
-#    stage: syn
-#    tags:
-#     - xilinx_ISE_14.7 
-#    script:
-#     - /entrypoint.sh
-#     - source ~/setup_ise147.sh
-#     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-#     - cd top/bare_top
-#     - python gen_sdbsyn.py --project wr_switch
-#     - cat synthesis_descriptor.vhd
-#     - cd ../../syn/scb_18ports 
-#     - hdlmake makefile 
-#     - make
-#    artifacts:
-#     name: SCB_TOP_8P_CI_$CI_JOB_ID
-#     paths:
-#     - syn/scb_18ports/*.syr
-#     - syn/scb_18ports/*.mrp
-#     - syn/scb_18ports/*.bit
-#     - syn/scb_18ports/*.bin
-#     - syn/scb_18ports/*.par
-#     - syn/scb_18ports/*.twr
+job_scb_top_18p_syn:
+   stage: syn
+   tags:
+    - xilinx_ISE_14.7 
+  # only:
+  #    refs:
+  #    - "wr-switch-sw-v*"
+  #    - "proposed_master"
+  #   - "master"
+   script:
+    - /entrypoint.sh
+    - source ~/setup_ise147.sh
+    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat synthesis_descriptor.vhd
+    - cd ../../modules/wrsw_hwiu
+    - python gen_ver.py
+    - cat gw_ver_pkg.vhd
+    - cd ../../syn/scb_18ports 
+    - hdlmake makefile 
+    - make
+   artifacts:
+    name: SCB_TOP_8P_CI_$CI_JOB_ID
+    paths:
+    - syn/scb_18ports/*.syr
+    - syn/scb_18ports/*.mrp
+    - syn/scb_18ports/*.bit
+    - syn/scb_18ports/*.bin
+    - syn/scb_18ports/*.par
+    - syn/scb_18ports/*.twr