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White Rabbit Switch - Gateware
Commit e8d3e8f3 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrsw_nic: update wb slave interface

parent a12e16b0
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Showing with 274 additions and 272 deletions
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @ e8d3e8f3
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd -- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb -- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Jan 12 17:37:53 2012 -- Created : Fri Jul 5 14:53:50 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...@@ -67,6 +67,7 @@ package nic_wbgen2_pkg is ...@@ -67,6 +67,7 @@ package nic_wbgen2_pkg is
); );
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers; function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package; end package;
package body nic_wbgen2_pkg is package body nic_wbgen2_pkg is
...@@ -78,15 +79,27 @@ else ...@@ -78,15 +79,27 @@ else
return x; return x;
end if; end if;
end function; end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers is function "or" (left, right: t_nic_in_registers) return t_nic_in_registers is
variable tmp: t_nic_in_registers; variable tmp: t_nic_in_registers;
begin begin
tmp.sr_bna_i := left.sr_bna_i or right.sr_bna_i; tmp.sr_bna_i := f_x_to_zero(left.sr_bna_i) or f_x_to_zero(right.sr_bna_i);
tmp.sr_rec_i := left.sr_rec_i or right.sr_rec_i; tmp.sr_rec_i := f_x_to_zero(left.sr_rec_i) or f_x_to_zero(right.sr_rec_i);
tmp.sr_tx_done_i := left.sr_tx_done_i or right.sr_tx_done_i; tmp.sr_tx_done_i := f_x_to_zero(left.sr_tx_done_i) or f_x_to_zero(right.sr_tx_done_i);
tmp.sr_tx_error_i := left.sr_tx_error_i or right.sr_tx_error_i; tmp.sr_tx_error_i := f_x_to_zero(left.sr_tx_error_i) or f_x_to_zero(right.sr_tx_error_i);
tmp.sr_cur_tx_desc_i := left.sr_cur_tx_desc_i or right.sr_cur_tx_desc_i; tmp.sr_cur_tx_desc_i := f_x_to_zero(left.sr_cur_tx_desc_i) or f_x_to_zero(right.sr_cur_tx_desc_i);
tmp.sr_cur_rx_desc_i := left.sr_cur_rx_desc_i or right.sr_cur_rx_desc_i; tmp.sr_cur_rx_desc_i := f_x_to_zero(left.sr_cur_rx_desc_i) or f_x_to_zero(right.sr_cur_rx_desc_i);
return tmp; return tmp;
end function; end function;
end package body; end package body;
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @ e8d3e8f3
This diff is collapsed.
modules/wrsw_nic/xwrsw_nic.vhd
View file @ e8d3e8f3
...@@ -17,7 +17,7 @@ entity xwrsw_nic is ...@@ -17,7 +17,7 @@ entity xwrsw_nic is
( (
g_interface_mode : t_wishbone_interface_mode := CLASSIC; g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD g_address_granularity : t_wishbone_address_granularity := WORD
); );
port ( port (
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -127,16 +127,17 @@ architecture rtl of xwrsw_nic is ...@@ -127,16 +127,17 @@ architecture rtl of xwrsw_nic is
component nic_wishbone_slave component nic_wishbone_slave
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(6 downto 0); wb_adr_i : in std_logic_vector(6 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_irq_o : out std_logic; wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_rcomp_i : in std_logic; irq_rcomp_i : in std_logic;
irq_rcomp_ack_o : out std_logic; irq_rcomp_ack_o : out std_logic;
irq_tcomp_i : in std_logic; irq_tcomp_i : in std_logic;
...@@ -290,16 +291,17 @@ begin -- rtl ...@@ -290,16 +291,17 @@ begin -- rtl
U_WB_SLAVE : nic_wishbone_slave U_WB_SLAVE : nic_wishbone_slave
port map ( port map (
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i, clk_sys_i => clk_sys_i,
wb_addr_i => wb_in.adr(6 downto 0), wb_adr_i => wb_in.adr(6 downto 0),
wb_data_i => wb_in.dat, wb_dat_i => wb_in.dat,
wb_data_o => wb_rdata_slave, wb_dat_o => wb_rdata_slave,
wb_cyc_i => wb_cyc_slave, wb_cyc_i => wb_cyc_slave,
wb_sel_i => wb_in.sel, wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb, wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we, wb_we_i => wb_in.we,
wb_ack_o => wb_ack_slave, wb_ack_o => wb_ack_slave,
wb_irq_o => wb_out.int, wb_stall_o => wb_out.stall,
wb_int_o => wb_out.int,
regs_o => regs_fromwb, regs_o => regs_fromwb,
......
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