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Grzegorz Daniluk authored
LVDS was too low for the discrete flip-flop. This was creating spikes on low half of the signal on some switches.
2d963063
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Manifest.py | ||
ext_pll_100_to_62m.vhd | ||
ext_pll_10_to_100.vhd | ||
oserdes_8_to_1.vhd | ||
pll200MhZ.vhd | ||
pll_62_5_500mhz.vhd |