Missed files, xdc cleaned differential pairs - again

0d41a88e · John Gill · d8fcce99 · 0d41a88e · 0d41a88e · 0d41a88e
Commit 0d41a88e authored Mar 31, 2020 by John Gill
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Showing with 74 additions and 58 deletions

wr2rf_maxdelays.tcl hdl/syn/wr2rf_maxdelays.tcl +15 -6

wr2rf_vme.tcl hdl/syn/wr2rf_vme.tcl +6 -0

wr2rf_vme.xdc hdl/syn/wr2rf_vme.xdc +53 -52

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--- a/hdl/syn/wr2rf_maxdelays.tcl
+++ b/hdl/syn/wr2rf_maxdelays.tcl
-foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
+set     endcells [get_cells -hier -filter {name=~*sync0_reg            && file_name=~*gc_sync.vhd}]
+lappend endcells [get_cells -hier -filter {name=~*dat_out_reg[*]       && file_name=~*gc_sync_word_wr.vhd}]
+lappend endcells [get_cells -hier -filter {name=~*data_out_o_reg[*]    && file_name=~*gc_sync_word_rd.vhd}]
+lappend endcells [get_cells -hier -filter {name=~*sync0_reg            && file_name=~*gc_sync_register.vhd}]
+
+# DEBUG
+foreach endcell [get_cells $endcells] {
+    puts $endcell
+}
+#return
+
+foreach endcell [get_cells $endcells] {
    set endclks [get_clocks -of_objects [get_cells $endcell]]

    if {$endclks eq ""} {
@@ -26,7 +37,7 @@ foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
 		set minstartperiod [tcl::mathfunc::min {*}$startperiods]
 		if {$minstartperiod < $minendperiod} {
 		    puts "WARNING: trying to synchronize a fast clock domain in slower clock domain"
-		    puts "WARNING: start: $minstartperiod end: $minendperiod"
+		    puts "WARNING: startPeriod: $minstartperiod endPeriod: $minendperiod"
 		}
 		set_max_delay -from $startcell -to $endcell -datapath_only $minendperiod 
 		puts "         StartCell: $startcell EndCell: $endcell"
@@ -41,7 +52,7 @@ foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
 		set minstartperiod [tcl::mathfunc::min {*}$startperiods]
 		if {$minstartperiod < $minendperiod} {
 		    puts "WARNING: trying to synchronize a fast clock domain in slower clock domain"
-		    puts "WARNING: Start: $minstartperiod End: $minendperiod"
+		    puts "WARNING: StartPeriod: $minstartperiod EndPeriod: $minendperiod"
 		}
 		set_max_delay -from $startport -to $endcell -datapath_only $minendperiod 
 		puts "         StartPort: $startport EndCell: $endcell"
@@ -51,7 +62,5 @@ foreach endcell [get_cells -hier -filter {name=~*sync_*edge.sync0_reg}] {
 	    puts "ERROR: unknown start class $startclass"
 	    error
 	}
-    }
-    
-		   
+    }	   
 }
--- a/hdl/syn/wr2rf_vme.tcl
+++ b/hdl/syn/wr2rf_vme.tcl
@@ -27,9 +27,12 @@ set start_time [clock seconds]
 synth_design -top ${top} -part ${device} > ${top}_synth.log
 write_checkpoint -force ${top}_synth

+source wr2rf_async_regs.tcl
+
 opt_design -directive Explore -verbose > ${top}_opt.log
 write_checkpoint -force ${top}_opt

+
 source wr2rf_maxdelays.tcl

 place_design -directive Explore > ${top}_place.log
@@ -41,6 +44,9 @@ write_checkpoint -force ${projDir}/${top}_phys_opt
 route_design -directive Explore > ${top}_route.log
 write_checkpoint -force ${projDir}/${top}_route

+source wr2rf_cdc_waivers.tcl
+report_cdc -name wr2rf_cdc -file wr2rf_cdc.rpt
+
 report_timing_summary -file ${top}_timing_summary.rpt
 report_timing -sort_by group -max_paths 100 -path_type full -file ${top}_timing.rpt
 report_utilization -hierarchical -file ${top}_utilization.rpt

--- a/hdl/syn/wr2rf_vme.xdc
+++ b/hdl/syn/wr2rf_vme.xdc
@@ -343,57 +343,56 @@ set_property direction OUT [get_ports {vme_retry_oe_o}]
 set_property direction IN [get_ports {vme_sysreset_n_i}]
 set_property direction IN [get_ports {vme_write_n_i}]
 set_property direction OUT [get_ports {clk_ext_10m_o}]
-make_diff_pair_ports clk_125m_gtx_p_i clk_125m_gtx_n_i
-make_diff_pair_ports clk_dmtd_62m5_p_i clk_dmtd_62m5_n_i
-make_diff_pair_ports clk_ext_10m_p_i clk_ext_10m_n_i
-make_diff_pair_ports clk_sys_62m5_p_i clk_sys_62m5_n_i
-make_diff_pair_ports dds_sync_p_o dds_sync_n_o
-make_diff_pair_ports rf1_iqdac_data_p_o[0] rf1_iqdac_data_n_o[0]
-make_diff_pair_ports rf1_iqdac_data_p_o[10] rf1_iqdac_data_n_o[10]
-make_diff_pair_ports rf1_iqdac_data_p_o[11] rf1_iqdac_data_n_o[11]
-make_diff_pair_ports rf1_iqdac_data_p_o[12] rf1_iqdac_data_n_o[12]
-make_diff_pair_ports rf1_iqdac_data_p_o[13] rf1_iqdac_data_n_o[13]
-make_diff_pair_ports rf1_iqdac_data_p_o[14] rf1_iqdac_data_n_o[14]
-make_diff_pair_ports rf1_iqdac_data_p_o[15] rf1_iqdac_data_n_o[15]
-make_diff_pair_ports rf1_iqdac_data_p_o[1] rf1_iqdac_data_n_o[1]
-make_diff_pair_ports rf1_iqdac_data_p_o[2] rf1_iqdac_data_n_o[2]
-make_diff_pair_ports rf1_iqdac_data_p_o[3] rf1_iqdac_data_n_o[3]
-make_diff_pair_ports rf1_iqdac_data_p_o[4] rf1_iqdac_data_n_o[4]
-make_diff_pair_ports rf1_iqdac_data_p_o[5] rf1_iqdac_data_n_o[5]
-make_diff_pair_ports rf1_iqdac_data_p_o[6] rf1_iqdac_data_n_o[6]
-make_diff_pair_ports rf1_iqdac_data_p_o[7] rf1_iqdac_data_n_o[7]
-make_diff_pair_ports rf1_iqdac_data_p_o[8] rf1_iqdac_data_n_o[8]
-make_diff_pair_ports rf1_iqdac_data_p_o[9] rf1_iqdac_data_n_o[9]
-make_diff_pair_ports rf1_iqdac_dci_p_o rf1_iqdac_dci_n_o
-make_diff_pair_ports rf1_sync_p_o rf1_sync_n_o
-make_diff_pair_ports rf1_t1_clk_p_i rf1_t1_clk_n_i
-make_diff_pair_ports rf1_t1_p_o rf1_t1_n_o
-make_diff_pair_ports rf1_t1_rst_p_o rf1_t1_rst_n_o
+#make_diff_pair_ports clk_125m_gtx_p_i clk_125m_gtx_n_i
+#make_diff_pair_ports clk_dmtd_62m5_p_i clk_dmtd_62m5_n_i
+#make_diff_pair_ports clk_ext_10m_p_i clk_ext_10m_n_i
+#make_diff_pair_ports clk_sys_62m5_p_i clk_sys_62m5_n_i
+#make_diff_pair_ports rf1_iqdac_data_p_o[0] rf1_iqdac_data_n_o[0]
+#make_diff_pair_ports rf1_iqdac_data_p_o[10] rf1_iqdac_data_n_o[10]
+#make_diff_pair_ports rf1_iqdac_data_p_o[11] rf1_iqdac_data_n_o[11]
+#make_diff_pair_ports rf1_iqdac_data_p_o[12] rf1_iqdac_data_n_o[12]
+#make_diff_pair_ports rf1_iqdac_data_p_o[13] rf1_iqdac_data_n_o[13]
+#make_diff_pair_ports rf1_iqdac_data_p_o[14] rf1_iqdac_data_n_o[14]
+#make_diff_pair_ports rf1_iqdac_data_p_o[15] rf1_iqdac_data_n_o[15]
+#make_diff_pair_ports rf1_iqdac_data_p_o[1] rf1_iqdac_data_n_o[1]
+#make_diff_pair_ports rf1_iqdac_data_p_o[2] rf1_iqdac_data_n_o[2]
+#make_diff_pair_ports rf1_iqdac_data_p_o[3] rf1_iqdac_data_n_o[3]
+#make_diff_pair_ports rf1_iqdac_data_p_o[4] rf1_iqdac_data_n_o[4]
+#make_diff_pair_ports rf1_iqdac_data_p_o[5] rf1_iqdac_data_n_o[5]
+#make_diff_pair_ports rf1_iqdac_data_p_o[6] rf1_iqdac_data_n_o[6]
+#make_diff_pair_ports rf1_iqdac_data_p_o[7] rf1_iqdac_data_n_o[7]
+#make_diff_pair_ports rf1_iqdac_data_p_o[8] rf1_iqdac_data_n_o[8]
+#make_diff_pair_ports rf1_iqdac_data_p_o[9] rf1_iqdac_data_n_o[9]
+#make_diff_pair_ports rf1_iqdac_dci_p_o rf1_iqdac_dci_n_o
+#make_diff_pair_ports rf1_sync_p_o rf1_sync_n_o
+#make_diff_pair_ports rf1_t1_clk_p_i rf1_t1_clk_n_i
+#make_diff_pair_ports rf1_t1_p_o rf1_t1_n_o
+#make_diff_pair_ports rf1_t1_rst_p_o rf1_t1_rst_n_o
 make_diff_pair_ports rf1_t2_clk_p_i rf1_t2_clk_n_i
-make_diff_pair_ports rf1_t2_p_o rf1_t2_n_o
-make_diff_pair_ports rf1_t2_rst_p_o rf1_t2_rst_n_o
-make_diff_pair_ports rf2_iqdac_data_p_o[0] rf2_iqdac_data_n_o[0]
-make_diff_pair_ports rf2_iqdac_data_p_o[10] rf2_iqdac_data_n_o[10]
-make_diff_pair_ports rf2_iqdac_data_p_o[11] rf2_iqdac_data_n_o[11]
-make_diff_pair_ports rf2_iqdac_data_p_o[12] rf2_iqdac_data_n_o[12]
-make_diff_pair_ports rf2_iqdac_data_p_o[13] rf2_iqdac_data_n_o[13]
-make_diff_pair_ports rf2_iqdac_data_p_o[14] rf2_iqdac_data_n_o[14]
-make_diff_pair_ports rf2_iqdac_data_p_o[15] rf2_iqdac_data_n_o[15]
-make_diff_pair_ports rf2_iqdac_data_p_o[1] rf2_iqdac_data_n_o[1]
-make_diff_pair_ports rf2_iqdac_data_p_o[2] rf2_iqdac_data_n_o[2]
-make_diff_pair_ports rf2_iqdac_data_p_o[3] rf2_iqdac_data_n_o[3]
-make_diff_pair_ports rf2_iqdac_data_p_o[4] rf2_iqdac_data_n_o[4]
-make_diff_pair_ports rf2_iqdac_data_p_o[5] rf2_iqdac_data_n_o[5]
-make_diff_pair_ports rf2_iqdac_data_p_o[6] rf2_iqdac_data_n_o[6]
-make_diff_pair_ports rf2_iqdac_data_p_o[7] rf2_iqdac_data_n_o[7]
-make_diff_pair_ports rf2_iqdac_data_p_o[8] rf2_iqdac_data_n_o[8]
-make_diff_pair_ports rf2_iqdac_data_p_o[9] rf2_iqdac_data_n_o[9]
-make_diff_pair_ports rf2_iqdac_dci_p_o rf2_iqdac_dci_n_o
-make_diff_pair_ports rf2_sync_p_o rf2_sync_n_o
-make_diff_pair_ports rf2_t1_clk_p_i rf2_t1_clk_n_i
-make_diff_pair_ports rf2_t1_p_o rf2_t1_n_o
-make_diff_pair_ports rf2_t1_rst_p_o rf2_t1_rst_n_o
-make_diff_pair_ports rf2_t2_clk_p_i rf2_t2_clk_n_i
+#make_diff_pair_ports rf1_t2_p_o rf1_t2_n_o
+#make_diff_pair_ports rf1_t2_rst_p_o rf1_t2_rst_n_o
+#make_diff_pair_ports rf2_iqdac_data_p_o[0] rf2_iqdac_data_n_o[0]
+#make_diff_pair_ports rf2_iqdac_data_p_o[10] rf2_iqdac_data_n_o[10]
+#make_diff_pair_ports rf2_iqdac_data_p_o[11] rf2_iqdac_data_n_o[11]
+#make_diff_pair_ports rf2_iqdac_data_p_o[12] rf2_iqdac_data_n_o[12]
+#make_diff_pair_ports rf2_iqdac_data_p_o[13] rf2_iqdac_data_n_o[13]
+#make_diff_pair_ports rf2_iqdac_data_p_o[14] rf2_iqdac_data_n_o[14]
+#make_diff_pair_ports rf2_iqdac_data_p_o[15] rf2_iqdac_data_n_o[15]
+#make_diff_pair_ports rf2_iqdac_data_p_o[1] rf2_iqdac_data_n_o[1]
+#make_diff_pair_ports rf2_iqdac_data_p_o[2] rf2_iqdac_data_n_o[2]
+#make_diff_pair_ports rf2_iqdac_data_p_o[3] rf2_iqdac_data_n_o[3]
+#make_diff_pair_ports rf2_iqdac_data_p_o[4] rf2_iqdac_data_n_o[4]
+#make_diff_pair_ports rf2_iqdac_data_p_o[5] rf2_iqdac_data_n_o[5]
+#make_diff_pair_ports rf2_iqdac_data_p_o[6] rf2_iqdac_data_n_o[6]
+#make_diff_pair_ports rf2_iqdac_data_p_o[7] rf2_iqdac_data_n_o[7]
+#make_diff_pair_ports rf2_iqdac_data_p_o[8] rf2_iqdac_data_n_o[8]
+#make_diff_pair_ports rf2_iqdac_data_p_o[9] rf2_iqdac_data_n_o[9]
+#make_diff_pair_ports rf2_iqdac_dci_p_o rf2_iqdac_dci_n_o
+#make_diff_pair_ports rf2_sync_p_o rf2_sync_n_o
+#make_diff_pair_ports rf2_t1_clk_p_i rf2_t1_clk_n_i
+#make_diff_pair_ports rf2_t1_p_o rf2_t1_n_o
+#make_diff_pair_ports rf2_t1_rst_p_o rf2_t1_rst_n_o
+#make_diff_pair_ports rf2_t2_clk_p_i rf2_t2_clk_n_i
 make_diff_pair_ports rf2_t2_p_o rf2_t2_n_o
 make_diff_pair_ports rf2_t2_rst_p_o rf2_t2_rst_n_o
 make_diff_pair_ports sfp1_rx_p_i sfp1_rx_n_i
@@ -1379,8 +1378,8 @@ create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRI
 create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK]

 # Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
-create_generated_clock -name clk_sys_bgmux  -divide_by 1      -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
-create_generated_clock -name clk_dmtd_bgmux -divide_by 1 -add -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
+create_generated_clock -name clk_sys_bgmux  -divide_by 1 -add -master_clock clk_sys  -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
+create_generated_clock -name clk_dmtd_bgmux -divide_by 1 -add -master_clock clk_dmtd -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]

 set_clock_groups -physically_exclusive -group clk_sys_bgmux -group clk_dmtd_bgmux

@@ -1403,6 +1402,8 @@ set_max_delay -from [get_cells inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen
 set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
 set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]

+set_false_path -from [get_cells -hier -filter {name=~*init_clock_ctrl_clk_sel_reg_reg}] -to [get_pins {inst_BUFGMUX_CTRL/S1}]
+

 #revert back to original instance
 current_instance -quiet