Scripts, mmcm for clk_sys62m5, maxdelays and cdc waiver infrastructure.

d8fcce99 · John Gill · 9bd051d8 · d8fcce99 · d8fcce99
Commit d8fcce99 authored Mar 31, 2020 by John Gill
Hide whitespace changes
Inline Side-by-side

Showing with 27 additions and 0 deletions

wr2rf_async_regs.tcl hdl/syn/wr2rf_async_regs.tcl +10 -0

wr2rf_cdc_waivers.tcl hdl/syn/wr2rf_cdc_waivers.tcl +17 -0

No files found.
--- a/hdl/syn/wr2rf_async_regs.tcl
+++ b/hdl/syn/wr2rf_async_regs.tcl
+# Every register in a synchroniser chain should be marked as a ASYNC_REG in the RTL.
+# Unfortunately not all are, and changing the RTL involves people, so we do it here 
+# in the constraints.
+
+set     need_async_reg [get_cells -hier -filter {name=~*_reg                               && file_name=~*dmtd_sampler.vhd}]
+lappend need_async_reg [get_cells -hier -filter {name=~*mdio_wr_spec_rx_cal_stat_sync*_reg && file_name=~*ep_pcs_tbi_mdio_wb.vhd}]
+
+set_property ASYNC_REG true [get_cells $need_async_reg]
+
+
--- a/hdl/syn/wr2rf_cdc_waivers.tcl
+++ b/hdl/syn/wr2rf_cdc_waivers.tcl
+create_waiver -type CDC -id CDC-13 \
+    -from [get_pins inst_core/inst_regs/init_clock_ctrl_clk_sel_reg_reg/C] \
+    -to   [get_pins inst_BUFGMUX_CTRL/S1] \
+    -user jgill \
+    -description "Select line on BUFGMUX timing not required."
+
+create_waiver -type CDC -id CDC-13 \
+    -from [get_pins inst_core/inst_regs/init_clock_ctrl_clk_sel_reg_reg/C] \
+    -to   [get_pins inst_BUFGMUX_CTRL/S0] \
+    -user jgill \
+    -description "Select line on BUFGMUX timing not required."
+
+create_waiver -type CDC -id CDC-10 \
+    -from [get_pins inst_BUFGMUX_CTRL/O] \
+    -to   [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}] \
+    -user jgill \
+    -description "Waiver combinational logic into dmtd_deglitch synchroniser - it comes from a Pads->ibfds->MMCM->bufgmux"