constraints again.

9bd051d8 · John Gill · c0061856 · 9bd051d8
Commit 9bd051d8 authored Mar 27, 2020 by John Gill
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Showing with 15 additions and 5 deletions

wr2rf_vme.xdc hdl/syn/wr2rf_vme.xdc +15 -5

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--- a/hdl/syn/wr2rf_vme.xdc
+++ b/hdl/syn/wr2rf_vme.xdc
@@ -1379,20 +1379,30 @@ create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRI
 create_clock -period 16.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK]

 # Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
-create_generated_clock -name clk_dmtd_bgmux -divide_by 1      -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]
-create_generated_clock -name clk_sys_bgmux  -divide_by 1 -add -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
+create_generated_clock -name clk_sys_bgmux  -divide_by 1      -source [get_ports {clk_sys_62m5_p_i}]  [get_pins {inst_BUFGMUX_CTRL/O}] 
+create_generated_clock -name clk_dmtd_bgmux -divide_by 1 -add -source [get_ports {clk_dmtd_62m5_p_i}] [get_pins {inst_BUFGMUX_CTRL/O}]

 set_clock_groups -physically_exclusive -group clk_sys_bgmux -group clk_dmtd_bgmux

 ###################
-# False paths
+# Critical paths
 ###################
-set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
-set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
+set_property ASYNC_REG true [get_cells -hier -filter {NAME=~*U_Sampler*gen_straight.clk_i_d*_reg}]
+set_max_delay -from [get_cells inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg] \
+	      -to   [get_cells inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d1_reg] \
+	      -datapath_only 1
+

 # False path all inputs to synchronizer (pos/negedge searching) registers - is there a better way?
 # set_false_path -to [get_cells -hier -filter {name=~*sync_posedge.sync0_reg}]
 # See wr2rf_maxdelays.tcl

+###################
+# False paths
+###################
+set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
+set_false_path -from [get_pins {inst_BUFGMUX_CTRL/O}] -to [get_pins {inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg/D}]
+
+
 #revert back to original instance
 current_instance -quiet