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wr2rf-vme
Commit c0061856 authored by Tristan Gingold's avatar Tristan Gingold
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Add init rf registers.

parent 28cb43c6
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Showing with 697 additions and 9 deletions
hdl/rtl/Manifest.py
View file @ c0061856
......@@ -8,5 +8,6 @@ files = ['vtu_blk.vhd',
'wr2rf_sysclks.vhd',
'wr2rf_rftrigger.vhd',
'wr2rf_rftrigger_regs.vhd',
'wr2rf_init_rf_regs.vhd',
'wr2rf_vme_p0.vhd',
'wr2rf_core.vhd', 'wr2rf_vme_regs.vhd']
hdl/rtl/gen_regs.sh
View file @ c0061856
......@@ -6,6 +6,8 @@ cheby -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
# Memory map for the trigger units
cheby -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
cheby -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
# Top-level memory map
cheby -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......
hdl/rtl/trigunit_regs.vhd
View file @ c0061856
-- Do not edit. Generated on Tue Mar 24 17:09:41 2020 by tgingold
-- Do not edit. Generated on Thu Mar 26 14:20:33 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/wr2rf_core.vhd
View file @ c0061856
......@@ -67,7 +67,29 @@ entity wr2rf_core is
pll_main_cs_n_o : out std_logic;
pll_main_sclk_o : out std_logic;
pll_main_sdi_o : out std_logic;
pll_main_sdo_i : in std_logic
pll_main_sdo_i : in std_logic;
-- RF 1
rf1_mux_sel_o : out std_logic_vector(1 downto 0);
rf1_mixer_en_o : out std_logic;
rf1_t1_delay_latch_o : out std_logic;
rf1_t1_delay_oen_o : out std_logic;
rf1_t1_mux_sel_o : out std_logic;
rf1_t2_delay_latch_o : out std_logic;
rf1_t2_delay_oen_o : out std_logic;
rf1_t2_mux_sel_o : out std_logic;
-- RF 2
rf2_mux_sel_o : out std_logic_vector(1 downto 0);
rf2_mixer_en_o : out std_logic;
rf2_t1_delay_latch_o : out std_logic;
rf2_t1_delay_oen_o : out std_logic;
rf2_t1_mux_sel_o : out std_logic;
rf2_t2_delay_latch_o : out std_logic;
rf2_t2_delay_oen_o : out std_logic;
rf2_t2_mux_sel_o : out std_logic;
rf_delay_o : out std_logic_vector(9 downto 0)
);
end;
......@@ -78,8 +100,14 @@ architecture arch of wr2rf_core is
signal rf_spi_in : t_wishbone_master_in;
signal rf_spi_out : t_wishbone_master_out;
signal rf_in : t_wishbone_master_in;
signal rf_out : t_wishbone_master_out;
signal wrpc_wb16_in : t_wishbone_master_in;
signal wrpc_wb16_out : t_wishbone_master_out;
signal rf1_t1_delay_data, rf1_t2_delay_data, rf2_t1_delay_data, rf2_t2_delay_data : std_logic_vector (15 downto 0);
signal rf1_t1_delay_wr, rf1_t2_delay_wr, rf2_t1_delay_wr, rf2_t2_delay_wr : std_logic;
begin
inst_regs: entity work.wr2rf_vme_regs
port map (
......@@ -107,6 +135,9 @@ begin
init_rf_spi_i => rf_spi_in,
init_rf_spi_o => rf_spi_out,
init_rf_i => rf_in,
init_rf_o => rf_out,
init_wrpc_i => wrpc_wb16_in,
init_wrpc_o => wrpc_wb16_out
);
......@@ -155,6 +186,55 @@ begin
pad_miso_i => pll_main_sdo_i
);
my_inst: entity work.wr2rf_init_rf_regs
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
wb_i => rf_out,
wb_o => rf_in,
rf1_common_mixer_en_o => rf1_mixer_en_o,
rf1_common_mux_sel_o => rf1_mux_sel_o,
rf1_ch_0_csr_delay_oen_o => rf1_t1_delay_oen_o,
rf1_ch_0_csr_mux_sel_o => rf1_t1_mux_sel_o,
rf1_ch_0_delay_o => rf1_t1_delay_data,
rf1_ch_0_delay_wr_o => rf1_t1_delay_wr,
rf1_ch_1_csr_delay_oen_o => rf1_t2_delay_oen_o,
rf1_ch_1_csr_mux_sel_o => rf1_t2_mux_sel_o,
rf1_ch_1_delay_o => rf1_t2_delay_data,
rf1_ch_1_delay_wr_o => rf1_t2_delay_wr,
rf2_common_mixer_en_o => rf2_mixer_en_o,
rf2_common_mux_sel_o => rf2_mux_sel_o,
rf2_ch_0_csr_delay_oen_o => rf2_t1_delay_oen_o,
rf2_ch_0_csr_mux_sel_o => rf2_t1_mux_sel_o,
rf2_ch_0_delay_o => rf2_t1_delay_data,
rf2_ch_0_delay_wr_o => rf2_t1_delay_wr,
rf2_ch_1_csr_delay_oen_o => rf2_t2_delay_oen_o,
rf2_ch_1_csr_mux_sel_o => rf2_t2_mux_sel_o,
rf2_ch_1_delay_o => rf2_t2_delay_data,
rf2_ch_1_delay_wr_o => rf2_t2_delay_wr
);
process(clk_i)
begin
if rising_edge(clk_i) then
if rf1_t1_delay_wr = '1' then
rf_delay_o <= rf1_t1_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf1_t2_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf2_t1_delay_data(9 downto 0);
elsif rf1_t2_delay_wr = '1' then
rf_delay_o <= rf2_t2_delay_data(9 downto 0);
else
rf_delay_o <= (others => '0');
end if;
rf1_t1_delay_latch_o <= rf1_t1_delay_wr;
rf1_t2_delay_latch_o <= rf1_t2_delay_wr;
rf2_t1_delay_latch_o <= rf2_t1_delay_wr;
rf2_t2_delay_latch_o <= rf2_t2_delay_wr;
end if;
end process;
inst_wb16x32: entity work.wb16_to_wb32
port map (
clk_i => clk_i,
......
hdl/rtl/wr2rf_init_regs.cheby
View file @ c0061856
......@@ -63,7 +63,10 @@ memory-map:
cs2: IQ DAC 2
filename: oc_spi16_regs.cheby
# TODO: interrupt controller.
# TODO: delays
- submap:
name: rf
description: Register for RF components
filename: wr2rf_init_rf_regs.cheby
- submap:
name: wrpc
interface: wb-16
......
hdl/rtl/wr2rf_init_rf_ch_regs.cheby 0 → 100644
View file @ c0061856
memory-map:
bus: wb-16
name: wr2rf_init_rf_regs
description: Memory map for the initialization part (edge compatible)
x-hdl:
busgroup: True
children:
- reg:
name: common
description: Control register for both channels
access: rw
width: 16
children:
- field:
name: mixer_en
range: 0
- field:
name: mux_sel
range: 2-1
- repeat:
name: ch
count: 2
children:
- reg:
name: csr
access: rw
width: 16
children:
- field:
name: delay_oen
range: 0
- field:
name: mux_sel
range: 1
- reg:
name: delay
access: wo
width: 16
x-hdl:
write-strobe: True
hdl/rtl/wr2rf_init_rf_regs.cheby 0 → 100644
View file @ c0061856
memory-map:
bus: wb-16
name: wr2rf_init_rf_regs
description: Memory map for rf chips
x-hdl:
busgroup: True
children:
- submap:
name: rf1
filename: wr2rf_init_rf_ch_regs.cheby
include: True
- submap:
name: rf2
filename: wr2rf_init_rf_ch_regs.cheby
include: True
hdl/rtl/wr2rf_init_rf_regs.vhd 0 → 100644
View file @ c0061856
This diff is collapsed.
hdl/rtl/wr2rf_rftrigger_regs.vhd
View file @ c0061856
-- Do not edit. Generated on Tue Mar 24 17:09:42 2020 by tgingold
-- Do not edit. Generated on Thu Mar 26 14:20:33 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/wr2rf_vme_regs.vhd
View file @ c0061856
-- Do not edit. Generated on Tue Mar 24 17:09:43 2020 by tgingold
-- Do not edit. Generated on Thu Mar 26 14:20:34 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -61,6 +61,10 @@ entity wr2rf_vme_regs is
init_rf_spi_i : in t_wishbone_master_in;
init_rf_spi_o : out t_wishbone_master_out;
-- Register for RF components
init_rf_i : in t_wishbone_master_in;
init_rf_o : out t_wishbone_master_out;
-- WR ptp core
init_wrpc_i : in t_wishbone_master_in;
init_wrpc_o : out t_wishbone_master_out
......@@ -121,6 +125,13 @@ architecture syn of wr2rf_vme_regs is
signal init_rf_spi_tr : std_logic;
signal init_rf_spi_wack : std_logic;
signal init_rf_spi_rack : std_logic;
signal init_rf_re : std_logic;
signal init_rf_we : std_logic;
signal init_rf_wt : std_logic;
signal init_rf_rt : std_logic;
signal init_rf_tr : std_logic;
signal init_rf_wack : std_logic;
signal init_rf_rack : std_logic;
signal init_wrpc_re : std_logic;
signal init_wrpc_we : std_logic;
signal init_wrpc_wt : std_logic;
......@@ -351,6 +362,28 @@ begin
init_rf_spi_o.we <= init_rf_spi_wt;
init_rf_spi_o.dat(15 downto 0) <= wr_dat_d0;
-- Interface init_rf
init_rf_tr <= init_rf_wt or init_rf_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
init_rf_rt <= '0';
init_rf_wt <= '0';
else
init_rf_rt <= (init_rf_rt or init_rf_re) and not init_rf_rack;
init_rf_wt <= (init_rf_wt or init_rf_we) and not init_rf_wack;
end if;
end if;
end process;
init_rf_o.cyc <= init_rf_tr;
init_rf_o.stb <= init_rf_tr;
init_rf_wack <= init_rf_i.ack and init_rf_wt;
init_rf_rack <= init_rf_i.ack and init_rf_rt;
init_rf_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 1)) & (0 downto 0 => '0');
init_rf_o.sel(1 downto 0) <= wr_sel_d0;
init_rf_o.we <= init_rf_wt;
init_rf_o.dat(15 downto 0) <= wr_dat_d0;
-- Interface init_wrpc
init_wrpc_tr <= init_wrpc_wt or init_wrpc_rt;
process (clk_i) begin
......@@ -374,7 +407,7 @@ begin
init_wrpc_o.dat(15 downto 0) <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_tmg_wack, init_pll_spi_wack, init_rf_spi_wack, init_wrpc_wack) begin
process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_tmg_wack, init_pll_spi_wack, init_rf_spi_wack, init_rf_wack, init_wrpc_wack) begin
ctrl_rf1_vtus_we <= '0';
ctrl_rf2_vtus_we <= '0';
ctrl_reg1_wreq <= '0';
......@@ -383,6 +416,7 @@ begin
init_tmg_wreq <= '0';
init_pll_spi_we <= '0';
init_rf_spi_we <= '0';
init_rf_we <= '0';
init_wrpc_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
......@@ -437,6 +471,10 @@ begin
-- Submap init_rf_spi
init_rf_spi_we <= wr_req_d0;
wr_ack_int <= init_rf_spi_wack;
when "000000000011" =>
-- Submap init_rf
init_rf_we <= wr_req_d0;
wr_ack_int <= init_rf_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
......@@ -450,13 +488,14 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_clock_status_mmcm_locked_i, init_tmg_io_term_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_io_dir_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_wrpc_i.dat, init_wrpc_rack) begin
process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_clock_status_mmcm_locked_i, init_tmg_io_term_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_io_dir_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack, init_wrpc_i.dat, init_wrpc_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
ctrl_rf1_vtus_re <= '0';
ctrl_rf2_vtus_re <= '0';
init_pll_spi_re <= '0';
init_rf_spi_re <= '0';
init_rf_re <= '0';
init_wrpc_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
......@@ -524,6 +563,11 @@ begin
init_rf_spi_re <= rd_req_int;
rd_dat_d0 <= init_rf_spi_i.dat(15 downto 0);
rd_ack_d0 <= init_rf_spi_rack;
when "000000000011" =>
-- Submap init_rf
init_rf_re <= rd_req_int;
rd_dat_d0 <= init_rf_i.dat(15 downto 0);
rd_ack_d0 <= init_rf_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
......
hdl/top/wr2rf_vme.vhd
View file @ c0061856
......@@ -227,7 +227,29 @@ entity wr2rf_vme is
pll_main_sdi_o : out std_logic;
pll_main_sdo_i : in std_logic;
pll_main_stat_i : in std_logic_vector(2 downto 1);
pll_main_sync_o : out std_logic
pll_main_sync_o : out std_logic;
-- RF 1
rf1_mux_sel_o : out std_logic_vector(1 downto 0);
rf1_mixer_en_o : out std_logic;
rf1_t1_delay_latch_o : out std_logic;
rf1_t1_delay_oen_o : out std_logic;
rf1_t1_mux_sel_o : out std_logic;
rf1_t2_delay_latch_o : out std_logic;
rf1_t2_delay_oen_o : out std_logic;
rf1_t2_mux_sel_o : out std_logic;
-- RF 2
rf2_mux_sel_o : out std_logic_vector(1 downto 0);
rf2_mixer_en_o : out std_logic;
rf2_t1_delay_latch_o : out std_logic;
rf2_t1_delay_oen_o : out std_logic;
rf2_t1_mux_sel_o : out std_logic;
rf2_t2_delay_latch_o : out std_logic;
rf2_t2_delay_oen_o : out std_logic;
rf2_t2_mux_sel_o : out std_logic;
rf_delay_o : out std_logic_vector(9 downto 0)
);
end wr2rf_vme;
......@@ -856,7 +878,28 @@ begin
pll_main_cs_n_o => pll_main_cs_n_o,
pll_main_sclk_o => pll_main_sclk_o,
pll_main_sdi_o => pll_main_sdi_o,
pll_main_sdo_i => pll_main_sdo_i
pll_main_sdo_i => pll_main_sdo_i,
rf1_mux_sel_o => rf1_mux_sel_o,
rf1_mixer_en_o => rf1_mixer_en_o,
rf1_t1_delay_latch_o => rf1_t1_delay_latch_o,
rf1_t1_delay_oen_o => rf1_t1_delay_oen_o,
rf1_t1_mux_sel_o => rf1_t1_mux_sel_o,
rf1_t2_delay_latch_o => rf1_t2_delay_latch_o,
rf1_t2_delay_oen_o => rf1_t2_delay_oen_o,
rf1_t2_mux_sel_o => rf1_t2_mux_sel_o,
rf2_mux_sel_o => rf2_mux_sel_o,
rf2_mixer_en_o => rf2_mixer_en_o,
rf2_t1_delay_latch_o => rf2_t1_delay_latch_o,
rf2_t1_delay_oen_o => rf2_t1_delay_oen_o,
rf2_t1_mux_sel_o => rf2_t1_mux_sel_o,
rf2_t2_delay_latch_o => rf2_t2_delay_latch_o,
rf2_t2_delay_oen_o => rf2_t2_delay_oen_o,
rf2_t2_mux_sel_o => rf2_t2_mux_sel_o,
rf_delay_o => rf_delay_o
);
-- timing_io
......
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