Add a register to control ext_ref_dir.

0fb8a3c4 · Tristan Gingold · 751ae006 · 0fb8a3c4 · 0fb8a3c4 · 0fb8a3c4
Commit 0fb8a3c4 authored May 20, 2020 by Tristan Gingold
6 changed files
--- a/hdl/rtl/wr2rf_core.vhd
+++ b/hdl/rtl/wr2rf_core.vhd
@@ -56,6 +56,7 @@ entity wr2rf_core is
        tmg_io_term_en_o  : out std_logic_vector(4 downto 1);
        tmg_clk_oe_o  : out std_logic_vector(1 downto 0);
        tmg_io_dir_o  : out std_logic;
+        ext_ref_dir_o : out std_logic;
        dds_cs_n_o         : out std_logic;
        rf1_iqdac_cs_n_o   : out std_logic;
@@ -63,7 +64,7 @@ entity wr2rf_core is
        rf_sclk_o          : out std_logic;
        rf_sdi_o           : out std_logic;
        rf_sdo_i           : in  std_logic;
        pll_main_cs_n_o : out std_logic;
        pll_main_sclk_o : out std_logic;
        pll_main_sdi_o  : out std_logic;
@@ -78,7 +79,7 @@ entity wr2rf_core is
        rf1_t2_delay_latch_o : out std_logic;
        rf1_t2_delay_oen_o   : out std_logic;
        rf1_t2_mux_sel_o     : out std_logic;
        --  RF 2
        rf2_mux_sel_o        : out std_logic_vector(1 downto 0);
        rf2_mixer_en_o       : out std_logic;
@@ -88,12 +89,12 @@ entity wr2rf_core is
        rf2_t2_delay_latch_o : out std_logic;
        rf2_t2_delay_oen_o   : out std_logic;
        rf2_t2_mux_sel_o     : out std_logic;
        rf_delay_o           : out std_logic_vector(9 downto 0);
        flash_cs_n_o         : out  std_logic;
        flash_mosi_o         : out  std_logic;
-        flash_miso_i         : in   std_logic    
+        flash_miso_i         : in   std_logic
    );
 end;
@@ -135,6 +136,7 @@ begin
        init_tmg_clk_term_o   => tmg_clk_term_en_o,
        init_tmg_clk_oe_o    => tmg_clk_oe_o,
        init_tmg_io_dir_o    => tmg_io_dir_o,
+        init_pin_ctrl_ext_ref_dir_o => ext_ref_dir_o,
        init_pll_spi_i => pll_spi_in,
        init_pll_spi_o => pll_spi_out,

--- a/hdl/rtl/wr2rf_init_regs.cheby
+++ b/hdl/rtl/wr2rf_init_regs.cheby
@@ -50,6 +50,17 @@ memory-map:
         name: io_dir
         description: bidirectional control for x4 general IO signals (not clocks)
         range: 10
+  - reg:
+      name: pin_ctrl
+      description: timing io grouping of signals
+      access: rw
+      width: 16
+      children:
+      - field:
+         name: ext_ref_dir
+         description: direction of clock 10Mhz connector
+         comment: "0: input, 1 : output"
+         range: 0
  - submap:
      name: pll_spi
      description: SPI master for the PLL

--- a/hdl/rtl/wr2rf_init_rf_regs.vhd
+++ b/hdl/rtl/wr2rf_init_rf_regs.vhd
-- Do not edit.  Generated on Mon May 04 16:51:42 2020 by gingold
+-- Do not edit.  Generated on Wed May 20 15:05:47 2020 by tgingold
 -- With Cheby 1.4.dev0 and these options:
 --  -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd

--- a/hdl/rtl/wr2rf_rftrigger_regs.vhd
+++ b/hdl/rtl/wr2rf_rftrigger_regs.vhd
-- Do not edit.  Generated on Mon May 04 16:51:42 2020 by gingold
+-- Do not edit.  Generated on Wed May 20 15:05:47 2020 by tgingold
 -- With Cheby 1.4.dev0 and these options:
 --  -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd

--- a/hdl/rtl/wr2rf_vme_regs.vhd
+++ b/hdl/rtl/wr2rf_vme_regs.vhd
-- Do not edit.  Generated on Mon May 04 16:51:42 2020 by gingold
+-- Do not edit.  Generated on Wed May 20 15:05:48 2020 by tgingold
 -- With Cheby 1.4.dev0 and these options:
 --  -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
@@ -49,6 +49,10 @@ entity wr2rf_vme_regs is
    -- bidirectional control for x4 general IO signals (not clocks)
    init_tmg_io_dir_o    : out   std_logic;
+    -- timing io grouping of signals
+    -- 0: input, 1 : output
+    init_pin_ctrl_ext_ref_dir_o : out   std_logic;
    -- SPI master for the PLL
    init_pll_spi_i       : in    t_wishbone_master_in;
    init_pll_spi_o       : out   t_wishbone_master_out;
@@ -115,6 +119,9 @@ architecture syn of wr2rf_vme_regs is
  signal init_tmg_io_dir_reg            : std_logic;
  signal init_tmg_wreq                  : std_logic;
  signal init_tmg_wack                  : std_logic;
+  signal init_pin_ctrl_ext_ref_dir_reg  : std_logic;
+  signal init_pin_ctrl_wreq             : std_logic;
+  signal init_pin_ctrl_wack             : std_logic;
  signal init_pll_spi_re                : std_logic;
  signal init_pll_spi_we                : std_logic;
  signal init_pll_spi_wt                : std_logic;
@@ -329,6 +336,22 @@ begin
    end if;
  end process;
+  -- Register init_pin_ctrl
+  init_pin_ctrl_ext_ref_dir_o <= init_pin_ctrl_ext_ref_dir_reg;
+  process (clk_i) begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        init_pin_ctrl_ext_ref_dir_reg <= '0';
+        init_pin_ctrl_wack <= '0';
+      else
+        if init_pin_ctrl_wreq = '1' then
+          init_pin_ctrl_ext_ref_dir_reg <= wr_dat_d0(0);
+        end if;
+        init_pin_ctrl_wack <= init_pin_ctrl_wreq;
+      end if;
+    end if;
+  end process;
  -- Interface init_pll_spi
  init_pll_spi_tr <= init_pll_spi_wt or init_pll_spi_rt;
  process (clk_i) begin
@@ -440,13 +463,14 @@ begin
  init_wrpc_o.dat(15 downto 0) <= wr_dat_d0;
  -- Process for write requests.
-  process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_tmg_wack, init_pll_spi_wack, init_rf_spi_wack, init_fw_update_wack, init_rf_wack, init_wrpc_wack) begin
+  process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_tmg_wack, init_pin_ctrl_wack, init_pll_spi_wack, init_rf_spi_wack, init_fw_update_wack, init_rf_wack, init_wrpc_wack) begin
    ctrl_rf1_vtus_we <= '0';
    ctrl_rf2_vtus_we <= '0';
    ctrl_reg1_wreq <= '0';
    ctrl_reg2_wreq <= '0';
    init_clock_ctrl_wreq <= '0';
    init_tmg_wreq <= '0';
+    init_pin_ctrl_wreq <= '0';
    init_pll_spi_we <= '0';
    init_rf_spi_we <= '0';
    init_fw_update_we <= '0';
@@ -494,6 +518,10 @@ begin
          -- Reg init_tmg
          init_tmg_wreq <= wr_req_d0;
          wr_ack_int <= init_tmg_wack;
+        when "0011" => 
+          -- Reg init_pin_ctrl
+          init_pin_ctrl_wreq <= wr_req_d0;
+          wr_ack_int <= init_pin_ctrl_wack;
        when others =>
          wr_ack_int <= wr_req_d0;
        end case;
@@ -526,7 +554,7 @@ begin
  end process;
  -- Process for read requests.
-  process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_clock_status_mmcm_locked_i, init_tmg_io_term_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_io_dir_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_fw_update_i.dat, init_fw_update_rack, init_rf_i.dat, init_rf_rack, init_wrpc_i.dat, init_wrpc_rack) begin
+  process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_clock_status_mmcm_locked_i, init_tmg_io_term_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_tmg_io_dir_reg, init_pin_ctrl_ext_ref_dir_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_fw_update_i.dat, init_fw_update_rack, init_rf_i.dat, init_rf_rack, init_wrpc_i.dat, init_wrpc_rack) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    ctrl_rf1_vtus_re <= '0';
@@ -589,6 +617,11 @@ begin
          rd_dat_d0(9 downto 8) <= init_tmg_clk_oe_reg;
          rd_dat_d0(10) <= init_tmg_io_dir_reg;
          rd_dat_d0(15 downto 11) <= (others => '0');
+        when "0011" => 
+          -- Reg init_pin_ctrl
+          rd_ack_d0 <= rd_req_int;
+          rd_dat_d0(0) <= init_pin_ctrl_ext_ref_dir_reg;
+          rd_dat_d0(15 downto 1) <= (others => '0');
        when others =>
          rd_ack_d0 <= rd_req_int;
        end case;

--- a/hdl/top/wr2rf_vme.vhd
+++ b/hdl/top/wr2rf_vme.vhd
@@ -85,6 +85,8 @@ entity wr2rf_vme is
    -- 10 MHz external reference clock.
    clk_ext_10m_p_i : in std_logic;
    clk_ext_10m_n_i : in std_logic;
+    clk_ext_10m_o   : out std_logic;
+    ext_ref_dir_o   : out std_logic;
    -- 62.5 MHz external reference clock (the above * 6.25)
 --    clk_ext_62m5_p_i : in std_logic;
@@ -217,7 +219,7 @@ entity wr2rf_vme is
    vme_p0_h2_lb2b_o   : out std_logic_vector(7 downto 0);
    vme_p0_h2_tc_o     : out std_logic;
    vme_p0_oen_o       : out std_logic;
    --  SPI
    dds_cs_n_o         : out std_logic;
    rf1_iqdac_cs_n_o   : out std_logic;
@@ -416,7 +418,7 @@ begin
            O  => clk_sys_62m5,               -- 1-bit output: Clock output
            I0 => clk_dmtd_62m5,              -- 1-bit input: Clock input (S=0)
 --            I1 => clk_sys_62m5_in,            -- 1-bit input: Clock input (S=1)
-            I1 => clk62m5,            -- 1-bit input: Clock input (S=1)            
+            I1 => clk62m5,            -- 1-bit input: Clock input (S=1)
            S  => clk_sys_select );           -- 1-bit input: Clock select
    inst_IBUFDS_clk_ext_10m : IBUFDS
@@ -850,21 +852,27 @@ begin
    port map (
      clk_i => clk_sys_62m5,
      rst_n_i => rst_sys_n,
-      mmcm_locked_i => mmcm_locked,
-      clk_sel_o => clk_sys_select,
-      clk_sys_reset_o => clk_sys_reset,
-      tmg_io_term_en_o => tmg_io_term_en_o,
-      tmg_clk_oe_o  => tmg_clk_oen_o,
-      tmg_io_dir_o  => tmg_io_dir,
      wb_i => master_out,
      wb_o => master_in,
+      wrc_wb_i => wrc_wb_out,
+      wrc_wb_o => wrc_wb_in,
      rf1_vtus_wb_i => rf1_vtus_wb_in,
      rf1_vtus_wb_o => rf1_vtus_wb_out,
      rf2_vtus_wb_i => rf2_vtus_wb_in,
      rf2_vtus_wb_o => rf2_vtus_wb_out,
-      wrc_wb_i => wrc_wb_out,
-      wrc_wb_o => wrc_wb_in,
+      mmcm_locked_i => mmcm_locked,
+      clk_sel_o => clk_sys_select,
+      clk_sys_reset_o => clk_sys_reset,
+      tmg_clk_term_en_o => tmg_clk_term_en_o,
+      tmg_io_term_en_o => tmg_io_term_en_o,
+      tmg_clk_oe_o  => tmg_clk_oen_o,
+      tmg_io_dir_o  => tmg_io_dir,
+      ext_ref_dir_o => ext_ref_dir_o,
      dds_cs_n_o => dds_cs_n_o,
      rf1_iqdac_cs_n_o => rf1_iqdac_cs_n_o,
@@ -872,13 +880,13 @@ begin
      rf_sclk_o => rf_sclk_o,
      rf_sdi_o => rf_sdi_o,
      rf_sdo_i => rf_sdo_i,
      pll_main_cs_n_o => pll_main_cs_n_o,
      pll_main_sclk_o => pll_main_sclk_o,
      pll_main_sdi_o => pll_main_sdi_o,
      pll_main_sdo_i => pll_main_sdo_i,
-      rf1_mux_sel_o => rf1_mux_sel_o, 
+      rf1_mux_sel_o => rf1_mux_sel_o,
      rf1_mixer_en_o => rf1_mixer_en_o,
      rf1_t1_delay_latch_o => rf1_t1_delay_latch_o,
      rf1_t1_delay_oen_o => rf1_t1_delay_oen_o,
@@ -886,8 +894,8 @@ begin
      rf1_t2_delay_latch_o => rf1_t2_delay_latch_o,
      rf1_t2_delay_oen_o => rf1_t2_delay_oen_o,
      rf1_t2_mux_sel_o => rf1_t2_mux_sel_o,
-      rf2_mux_sel_o => rf2_mux_sel_o, 
+      rf2_mux_sel_o => rf2_mux_sel_o,
      rf2_mixer_en_o => rf2_mixer_en_o,
      rf2_t1_delay_latch_o => rf2_t1_delay_latch_o,
      rf2_t1_delay_oen_o => rf2_t1_delay_oen_o,
@@ -895,7 +903,7 @@ begin
      rf2_t2_delay_latch_o => rf2_t2_delay_latch_o,
      rf2_t2_delay_oen_o => rf2_t2_delay_oen_o,
      rf2_t2_mux_sel_o => rf2_t2_mux_sel_o,
      rf_delay_o => rf_delay_o,
      flash_cs_n_o => spi_flash_cs_n_o,