vtuCore: improve style.

2236321a · Tristan Gingold · 16df5e32 · 2236321a
Commit 2236321a authored Apr 23, 2020 by Tristan Gingold
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Showing with 8 additions and 6 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +8 -6

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -1313,27 +1313,29 @@ architecture vtuCore of vtuCore is
  signal visual_B_SwitchHTFF_Q : std_logic;

 begin
+  --  Data shifter using B parameters: from Sync pulse to the first pulse.
  B_DataShifterB: entity work.vtuDataShifter
    generic map (N => 64,
                 g_DisableDoubleSync => '1')
    port map (CoarseZero => BCoarseZero,
-              DataOut => DataOut_1(7 downto 0),
+              DataOut => DataOut_1,
              OutputEnabled => OE_1,
              Clk => Clk,
-              Delay => bValue(63 downto 0),
-              DataIn => DataIn(7 downto 0),
+              Delay => bValue,
+              DataIn => DataIn,
              Enabled => Shifter1Ena,
              SyncPulse => SyncPulse_i);

+  --  Data shifter using HT parameters: after the first pulse.
  B_DataShifterHT: entity work.vtuDataShifter
    generic map (N => 64,
                 g_DisableDoubleSync => '0')
    port map (CoarseZero => HTCoarseZero,
-              DataOut => DataOut_2(7 downto 0),
+              DataOut => DataOut_2,
              OutputEnabled => OE_2,
              Clk => Clk,
-              Delay => htValue_effective(63 downto 0),
-              DataIn => DataIn_2(7 downto 0),
+              Delay => htValue_effective,
+              DataIn => DataIn_2,
              Enabled => Shifter2Ena,
              SyncPulse => open);