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wr2rf-vme
Commit 483953bb authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: simplify HDL.

parent 93d483df
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Showing with 7 additions and 19 deletions
dependencies/vtu/rtl/vtuCore.vhd
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...@@ -1222,13 +1222,11 @@ architecture vtuCore of vtuCore is ...@@ -1222,13 +1222,11 @@ architecture vtuCore of vtuCore is
signal wrongValue : std_logic; signal wrongValue : std_logic;
signal SwitchHTeffective_n : std_logic; signal SwitchHTeffective_n : std_logic;
signal ClkValueSwitch_n : std_logic; signal ClkValueSwitch_n : std_logic;
signal CZero : std_logic_vector(63 downto 0 );
signal SyncLessEna : std_logic; signal SyncLessEna : std_logic;
signal DataOutLowFreq : std_logic_vector(7 downto 0 ); signal DataOutLowFreq : std_logic_vector(7 downto 0 );
signal DataIn_2 : std_logic_vector(7 downto 0 ); signal DataIn_2 : std_logic_vector(7 downto 0 );
signal Shifter2Ena : std_logic; signal Shifter2Ena : std_logic;
signal DataInHTSyncLess : std_logic_vector(7 downto 0 ); signal DataInHTSyncLess : std_logic_vector(7 downto 0 );
signal AllOneOut : std_logic_vector(7 downto 0 );
signal WindowDone : std_logic; signal WindowDone : std_logic;
signal wValueOne_seq : std_logic; signal wValueOne_seq : std_logic;
signal BCoarseZero : std_logic; signal BCoarseZero : std_logic;
...@@ -1270,7 +1268,6 @@ architecture vtuCore of vtuCore is ...@@ -1270,7 +1268,6 @@ architecture vtuCore of vtuCore is
signal DataOutHTSyncLess : std_logic_vector(7 downto 0 ); signal DataOutHTSyncLess : std_logic_vector(7 downto 0 );
signal htValuePlusOne : std_logic_vector(63 downto 0 ); signal htValuePlusOne : std_logic_vector(63 downto 0 );
signal SyncLessOperationMode : std_logic; signal SyncLessOperationMode : std_logic;
signal AllZeroOut : std_logic_vector(7 downto 0 );
signal Start_i : std_logic; signal Start_i : std_logic;
signal Mem_RdDataZero : std_logic_vector(7 downto 0 ) := (others => '0'); signal Mem_RdDataZero : std_logic_vector(7 downto 0 ) := (others => '0');
signal Run_seq : std_logic; signal Run_seq : std_logic;
...@@ -1285,7 +1282,6 @@ architecture vtuCore of vtuCore is ...@@ -1285,7 +1282,6 @@ architecture vtuCore of vtuCore is
signal RunPlayMem : std_logic; signal RunPlayMem : std_logic;
signal PlayingMem : std_logic; signal PlayingMem : std_logic;
signal Stop_seq : std_logic; signal Stop_seq : std_logic;
signal SyncLessStartData : std_logic_vector(7 downto 0 );
signal Start_seq : std_logic; signal Start_seq : std_logic;
signal DataOut_1 : std_logic_vector(7 downto 0 ); signal DataOut_1 : std_logic_vector(7 downto 0 );
signal SetPlayingMem : std_logic; signal SetPlayingMem : std_logic;
...@@ -1571,8 +1567,6 @@ begin ...@@ -1571,8 +1567,6 @@ begin
end if; end if;
end process; end process;
CZero(63 downto 0) <= (others => '0');
WindowDone_seq <= WindowDone and (not InfiniteWindow); WindowDone_seq <= WindowDone and (not InfiniteWindow);
counterEnable <= (OE_1 or OE_2) and Run_seq; counterEnable <= (OE_1 or OE_2) and Run_seq;
...@@ -1581,18 +1575,16 @@ begin ...@@ -1581,18 +1575,16 @@ begin
InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode; InfiniteWindow <= InfiniteWindowMode or LowFreqGenerationMode;
process (DataOutHTSyncLess , SyncLessStartData , SetStartData) process (DataOutHTSyncLess, SetStartData)
begin begin
case SetStartData is case SetStartData is
when '0' => when '0' =>
DataInHTSyncLess <= DataOutHTSyncLess; DataInHTSyncLess <= DataOutHTSyncLess;
when others => when others =>
DataInHTSyncLess <= SyncLessStartData; DataInHTSyncLess <= x"01";
end case; end case;
end process; end process;
SyncLessStartData(7 downto 0) <= X"01";
StartSyncLess <= Start and SyncLessOperationMode; StartSyncLess <= Start and SyncLessOperationMode;
SyncLessDisabled <= not SyncLessEna; SyncLessDisabled <= not SyncLessEna;
...@@ -1615,13 +1607,13 @@ begin ...@@ -1615,13 +1607,13 @@ begin
or DataOut_seq(4) or DataOut_seq(3) or DataOut_seq(2) or DataOut_seq(4) or DataOut_seq(3) or DataOut_seq(2)
or DataOut_seq(1) or DataOut_seq(0); or DataOut_seq(1) or DataOut_seq(0);
process (AllZeroOut , AllOneOut , ClkValueSwitch) process (ClkValueSwitch)
begin begin
case ClkValueSwitch is case ClkValueSwitch is
when '0' => when '0' =>
DataAllEqual(7 downto 0) <= AllZeroOut(7 downto 0); DataAllEqual <= (others => '0');
when others => when others =>
DataAllEqual(7 downto 0) <= AllOneOut(7 downto 0); DataAllEqual <= (others => '1');
end case; end case;
end process; end process;
...@@ -1629,16 +1621,12 @@ begin ...@@ -1629,16 +1621,12 @@ begin
begin begin
case FilledMuxSel is case FilledMuxSel is
when '0' => when '0' =>
DataOutLowFreq(7 downto 0) <= DataAllEqual(7 downto 0); DataOutLowFreq <= DataAllEqual;
when others => when others =>
DataOutLowFreq(7 downto 0) <= DataFilled(7 downto 0); DataOutLowFreq <= DataFilled;
end case; end case;
end process; end process;
AllZeroOut(7 downto 0) <= (others => '0');
AllOneOut(7 downto 0) <= (others => '1');
-- Fill data with ones or zeros after one when DataOutPulse='1' -- Fill data with ones or zeros after one when DataOutPulse='1'
process(DataOut_seq, DataOutPulse, ClkValueSwitch) process(DataOut_seq, DataOutPulse, ClkValueSwitch)
begin begin
......
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