vtuCore: remove htValuePlusOne. Cleanup.

4fc725b8 · Tristan Gingold · 60809b52 · 4fc725b8
Commit 4fc725b8 authored Apr 23, 2020 by Tristan Gingold
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vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +8 -92

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -817,78 +817,6 @@ begin
 end vtuSeq;
----------------------------------------------------
--
--  Library Name :  CommonVisual
--  Unit    Name :  LimAdderN
--  Unit    Type :  Text Unit
--
------------------------------------------------------
--------------------------------------------------------------------
--------------------------------------------------------------------
-- Date        : Thu Oct 22 15:44:29 2009
--
-- Author      : Gregoire Hagmann
--
-- Company     : CERN BE/RF/FB
--
-- Description : Adder with signed data bus and limiter circuitry
--
--------------------------------------------------------------------
--------------------------------------------------------------------
-library ieee;
-use ieee.STD_LOGIC_1164.all;
-library ieee;
-use ieee.NUMERIC_STD.all;
-entity  LimAdderN  is
-port (A : in std_logic_vector; --vector size defined by the signals connected to the block
-      B : in std_logic_vector ;
-      lim : out std_logic;
-      O : out std_logic_vector);
-end;
--------------------------------------------------------------------
--------------------------------------------------------------------
-- Date        : Thu Oct 22 15:44:29 2009
--
-- Author      : Gregoire Hagmann
--
-- Company     : CERN BE/RF/FB
--
-- Description : Adder with signed data bus and limiter circuitry
--
--------------------------------------------------------------------
--------------------------------------------------------------------
-architecture  V1  of  LimAdderN  is
-    signal l_sum : std_logic_vector(O'length downto 0):=(others => '0'); --default value for simulation only
-    constant c_ValMax : std_logic_vector(O'range):=('0',others => '1');
-    constant c_ValMin : std_logic_vector(O'range):=('1',others => '0');
-begin
-    process(l_sum)
-    begin
-        if l_sum(O'length)='0' and l_sum(O'length-1)='1' then
-            --Val max positive
-            O <= c_ValMax;
-            Lim <= '1';
-        elsif l_sum(O'length)='1' and l_sum(O'length-1)='0' then
-            --Val max negative
-            O <= c_ValMin;
-            Lim <= '1';
-        else
-            O <= l_sum(O'length-1 downto 0);
-            Lim <= '0';
-        end if;
-    end process;
-    l_sum <= std_logic_vector(resize(signed(A),O'length+1) + resize(signed(B),O'length+1));
-end;
 library ieee;
 use ieee.STD_LOGIC_1164.all;
@@ -913,13 +841,9 @@ end WrongValuesLogic;
 architecture WrongValuesLogic of WrongValuesLogic is
 begin
-  WrongValuesLogic:
  process (Clk)
  begin
    if rising_edge(Clk) then
      if Rst = '1' then
        wrongB <= '1';
@@ -998,7 +922,7 @@ begin
        end if ;
      end if ;
    end if ;
-  end process WrongValuesLogic;
+  end process;
 end WrongValuesLogic;
@@ -1017,15 +941,11 @@ entity ModeSelDecoder is
        LowFreqGenerationMode : out std_logic;
        PlayMemoryMode : out std_logic
        );
 end ModeSelDecoder;
 architecture ModeSelDecoder of ModeSelDecoder is
 begin
-  ModeSelDecoder:
  process (Mode)
  begin
@@ -1079,15 +999,16 @@ begin
      LowFreqGenerationMode <= '0';
      PlayMemoryMode <= '0';
    end if ;
-  end process ModeSelDecoder;
+  end process;
 end ModeSelDecoder;
 library ieee;
 use ieee.STD_LOGIC_1164.all;
 use ieee.NUMERIC_STD.all;
 library work;
 use work.MemMap_ctuAsVtu.all;
 entity vtuCore is
  port (
    --  Interface to the memory for the play memory mode.
@@ -1191,7 +1112,6 @@ architecture vtuCore of vtuCore is
  signal InfiniteWindow : std_logic;
  signal DataOut_seq : std_logic_vector(7 downto 0 );
  signal DataOutHTSyncLess : std_logic_vector(7 downto 0 );
-  signal htValuePlusOne : std_logic_vector(63 downto 0 );
  signal SyncLessOperationMode : std_logic;
  signal Start_i : std_logic;
  signal Mem_RdDataZero : std_logic_vector(7 downto 0 ) := (others  => '0');
@@ -1343,12 +1263,6 @@ begin
              Clk => Clk,
              Rst => Rst);
-  B_LimAdder: entity work.LimAdderN
-    port map (A => htValue(63 downto 0),
-              B => COne(63 downto 0),
-              lim => open,
-              O => htValuePlusOne(63 downto 0));
  wrongValue <= wrongB_s or wrongHT_s or wrongW_s;
  wrongB <= wrongB_s;
@@ -1399,13 +1313,15 @@ begin
  --  Pulse detected.
  SyncPulse <= SyncPulse_i;
-  process (htValue, htValuePlusOne, SwitchHTeffective)
+  process (htValue, SwitchHTeffective)
  begin
     case SwitchHTeffective is
       when '0' =>
         htValue_effective <=  htValue;
       when others =>
-         htValue_effective <=  htValuePlusOne;
+         --  Do not care about overflow in the addition.  It can only happen when htValue is ffff_ffff_ffff_ffff,
+         --  and thus the switch happen after the end of the universe.
+         htValue_effective <=  std_logic_vector(unsigned(htValue) + 1);
     end case;
   end process;