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wr2rf-vme
Commit 92676136 authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: reformat vtuSeq.

parent bd08f811
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Showing with 50 additions and 41 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ 92676136
......@@ -780,114 +780,123 @@ entity vtuSeq is
CounterRst : out std_logic := '0';
Run : out std_logic := '0'
);
end vtuSeq;
architecture vtuSeq of vtuSeq is
type visual_Idle_states is (Idle, S_BValue, S_HTValue, S_waitSync);
signal visual_Idle_current : visual_Idle_states;
type visual_Idle_states is
(
Idle,
S_waitSync,
S_BValue,
S_HTValue
);
signal state : visual_Idle_states;
begin
-- Synchronous process
vtuSeq_Idle:
process (Clk)
begin
if (rising_edge(Clk)) then
if (Rst = '1' or Stop = '1') then
if rising_edge(Clk) then
if Rst = '1' or Stop = '1' then
-- Reset (or stop): back to idle.
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= Idle;
state <= Idle;
else
case visual_Idle_current is
case state is
when Idle =>
if (Start = '1' and SyncPulse = '0') then
if Start = '1' and SyncPulse = '0' then
-- Wait for Sync.
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '0';
Run <= '0';
visual_Idle_current <= S_waitSync;
elsif (Start = '1' and SyncPulse = '1') then
state <= S_waitSync;
elsif Start = '1' and SyncPulse = '1' then
-- Start and sync: directly run.
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '0';
CounterRst <= '0';
Run <= '1';
visual_Idle_current <= S_BValue;
state <= S_BValue;
else
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '0';
Run <= '0';
visual_Idle_current <= Idle;
state <= Idle;
end if;
when S_waitSync =>
if SyncPulse = '1' then
-- Run.
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '0';
CounterRst <= '0';
Run <= '1';
state <= S_BValue;
else
CounterRst <= '0';
state <= S_waitSync;
end if;
when S_BValue =>
if (OutputEnable1 = '1' and wValueOne = '0') then
if OutputEnable1 = '1' and wValueOne = '0' then
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '1';
CounterRst <= '0';
visual_Idle_current <= S_HTValue;
elsif (OutputEnable1 = '1' and wValueOne = '1') then
state <= S_HTValue;
elsif OutputEnable1 = '1' and wValueOne = '1' then
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= Idle;
elsif (Start = '1' and SyncPulse = '0') then
state <= Idle;
elsif Start = '1' and SyncPulse = '0' then
-- Restart, wait for sync
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= S_waitSync;
elsif (Start = '1' and SyncPulse = '1') then
state <= S_waitSync;
elsif Start = '1' and SyncPulse = '1' then
-- Restart, run.
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '0';
CounterRst <= '1';
visual_Idle_current <= S_BValue;
state <= S_BValue;
else
CounterRst <= '0';
visual_Idle_current <= S_BValue;
state <= S_BValue;
end if;
when S_HTValue =>
if (OutputEnable2 = '1' and WindowDone = '1') then
if OutputEnable2 = '1' and WindowDone = '1' then
-- Done.
Shifter1Ena <= '1';
Shifter2Ena <= '0';
SwitchtoHT <= '0';
CounterRst <= '1';
Run <= '0';
visual_Idle_current <= Idle;
state <= Idle;
else
visual_Idle_current <= S_HTValue;
end if;
when S_waitSync =>
if (SyncPulse = '1') then
Shifter1Ena <= '1';
Shifter2Ena <= '1';
SwitchtoHT <= '0';
CounterRst <= '0';
Run <= '1';
visual_Idle_current <= S_BValue;
else
CounterRst <= '0';
visual_Idle_current <= S_waitSync;
state <= S_HTValue;
end if;
when others =>
visual_Idle_current <= Idle;
state <= Idle;
end case;
end if;
end if;
......
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