testbench: minor adjustments (including clock).

a924ab6e · Tristan Gingold · 9a2e4bdd · a924ab6e · a924ab6e
Commit a924ab6e authored Apr 01, 2020 by Tristan Gingold
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Showing with 25 additions and 18 deletions

Manifest.py hdl/testbench/vtu/Manifest.py +3 -1

tb_vtu.vhd hdl/testbench/vtu/tb_vtu.vhd +22 -17

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--- a/hdl/testbench/vtu/Manifest.py
+++ b/hdl/testbench/vtu/Manifest.py
@@ -4,4 +4,6 @@ files = ['tb_vtu.vhd', 'sim_wishbone.vhd', 'trigunit_regs_consts.vhd', 'vtudiag_
 fetchto = "../../dependencies"
 modules = {'local': [ '../../rtl' ],
           'git': [ "git://ohwr.org/project/general-cores.git",
-                    "git://ohwr.org/project/vme64x-core.git"]  }
+#                    "git://ohwr.org/project/vme64x-core.git"
+                  ]
+          }
--- a/hdl/testbench/vtu/tb_vtu.vhd
+++ b/hdl/testbench/vtu/tb_vtu.vhd
@@ -12,25 +12,33 @@ end tb_vtu;
 architecture arch of tb_vtu is
    signal clk_sys : std_logic := '0';
    signal rst_sys : std_logic;
-    signal clk_refclk : std_logic := '0';
-    signal rf_clk_n : std_logic := '0';
-    signal rf_clk_p : std_logic := '1';

-    signal sync_n, sync_p, sync : std_logic := '0';
-    signal trig_n, trig_p : std_logic := '0';
+    signal clk_rf : std_logic := '0';
+    signal clk_vtu : std_logic := '0';
+
+    signal sync : std_logic := '0';
+    signal trig_p : std_logic := '0';
    signal start, stop : std_logic := '0';

    signal wb_in : t_wishbone_slave_in;
    signal wb_out : t_wishbone_slave_out;
 begin
+    --  System clock, 62.5 Mhz
    clk_sys <= not clk_sys after 8 ns;
    rst_sys <= '1', '0' after 16 ns;
-    clk_refclk <= not clk_refclk after 2.5 ns;
-    rf_clk_n <= not rf_clk_n after 2.5 ns;
-    rf_clk_p <= not rf_clk_p after 2.5 ns;

-    sync_n <= not sync;
-    sync_p <= sync;
+    --  RF clock, ~200Mhz
+    process
+      variable cnt : natural := 8;
+    begin
+      clk_rf <= not clk_rf;
+      if cnt = 8 then
+        clk_vtu <= not clk_vtu;
+        cnt := 0;
+      end if;
+      cnt := cnt + 1;
+      wait for 2.5 ns;
+    end process;

    my_inst: entity work.vtu_blk
      port map (
@@ -38,13 +46,10 @@ begin
        rst_sys_i => rst_sys,
        wb_i => wb_in,
        wb_o => wb_out,
-        clk_refclk => clk_refclk,
-        rf_clk_n_i => rf_clk_n,
-        rf_clk_p_i => rf_clk_p,
-        sync_n_i => sync_n,
-        sync_p_i => sync_p,
-        trig_n_o => trig_n,
-        trig_p_o => trig_p,
+        clk_vtu_i => clk_vtu,
+        clk_rf_i => clk_rf,
+        sync_i => sync,
+        trig_o => trig_p,
        start_i => start,
        stop_i => stop
      );