Skip to content

W
wr2rf-vme
Commit b7dfe48d authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

vtuCore: simplify logic.

parent 5e15b48f
Hide whitespace changes
Inline Side-by-side
Showing with 14 additions and 28 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ b7dfe48d
......@@ -574,9 +574,6 @@ architecture vtuDataShifter of vtuDataShifter is
Q : out std_logic
);
end component;
signal visual_B_Counter_cur_state : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_Counter_next_state : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_Counter_next_count : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_CoarseDly_sub_dif_int : std_logic_vector((N - 4) + 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_a : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_b : std_logic_vector((N - 4) + 1 - 1 downto 0 );
......@@ -598,30 +595,20 @@ begin
DataIn_clean <= clean_data(DataIn);
Sync_i <= DataIn_clean(7) or DataIn_clean(6) or DataIn_clean(5)
or DataIn_clean(4) or DataIn_clean(3) or DataIn_clean(2)
or DataIn_clean(1) or DataIn_clean(0);
CoarseCnt(N-4 downto 0) <= (visual_B_Counter_cur_state);
visual_B_Counter_next_state <= visual_B_Counter_next_count;
-- Set if at least one bit is set.
Sync_i <= '1' when DataIn /= b"0000_0000" else '0';
process (Clk)
begin
if (Clk'event and Clk = '1') then
if CntRst = '1' then
visual_B_Counter_cur_state <= (others => '0');
CoarseCnt <= (others => '0');
else
visual_B_Counter_cur_state <= visual_B_Counter_next_state;
CoarseCnt <= std_logic_vector(unsigned (CoarseCnt) + 1);
end if;
end if;
end process;
process (visual_B_Counter_cur_state )
begin
visual_B_Counter_next_count <= std_logic_vector(unsigned (visual_B_Counter_cur_state) + 1);
end process;
CoarseDly_i(N-4 downto 0) <= Delay(N-1 downto 3);
FineDly(2 downto 0) <= Delay(2 downto 0);
......@@ -650,13 +637,13 @@ begin
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (SyncPulse_i = '1') then
if SyncPulse_i = '1' then
DataClean(7 downto 0) <= (DataIn_clean(7 downto 0));
end if;
end if;
end process;
process (OutGood , OutGoodNext , UseNextValue)
process (OutGood, OutGoodNext, UseNextValue)
begin
case UseNextValue is
when '0' =>
......@@ -666,13 +653,12 @@ begin
end case;
end process;
ShiftReg_proc: process(DataRaw, FineDly)
ShiftReg_proc: process (DataRaw, FineDly)
variable DataOut_aux : std_logic_vector(15 downto 0);
begin
DataOut_aux(15 downto 0) := std_logic_vector(shift_right(unsigned(DataRaw),
to_integer(unsigned(FineDly))));
DataOut_aux(15 downto 0) := std_logic_vector(shift_right(unsigned(DataRaw), to_integer(unsigned(FineDly))));
UseNextValue <= or_reduce(DataOut_aux(7 downto 0));
if or_reduce(DataOut_aux(7 downto 0))='0' then
if or_reduce(DataOut_aux(7 downto 0)) = '0' then
DataOut_i(7 downto 0) <= DataOut_aux(15 downto 8);
else
DataOut_i(7 downto 0) <= DataOut_aux(7 downto 0);
......@@ -689,13 +675,13 @@ begin
process (Clk)
begin
if (Clk'event and Clk = '1') then
Sync_prev <= (Sync_i);
Sync_prev <= Sync_i;
end if;
end process;
OutGood <= ( CoarseGood) and ( Ready);
OutGood <= CoarseGood and Ready;
process (CoarseDly_i , CZeroDly)
process (CoarseDly_i, CZeroDly)
begin
if CoarseDly_i(N-4 downto 0) = CZeroDly(N-4 downto 0) then
CoarseZero_i <= '1';
......@@ -710,8 +696,8 @@ begin
visual_B_CoarseDly_sub_tmp_a <= (CoarseDly_i(N-4 downto 0));
visual_B_CoarseDly_sub_tmp_b <= (COne(N-4 downto 0));
visual_B_CoarseDly_sub_dif_int <= std_logic_vector((unsigned('0' &
visual_B_CoarseDly_sub_tmp_a) - unsigned('0' & visual_B_CoarseDly_sub_tmp_b)));
visual_B_CoarseDly_sub_dif_int <= std_logic_vector
((unsigned('0' & visual_B_CoarseDly_sub_tmp_a) - unsigned('0' & visual_B_CoarseDly_sub_tmp_b)));
CoarseDly(N-4 downto 0) <= visual_B_CoarseDly_sub_dif_int((N-4) + 1 - 1 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment