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wr2rf-vme
Commit f4679007 authored by Tristan Gingold's avatar Tristan Gingold
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vtu: add online registers.

parent 4d1219e4
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Showing with 118 additions and 17 deletions
hdl/rtl/trigunit_regs.cheby
View file @ f4679007
......@@ -131,7 +131,10 @@ memory-map:
range: 1
- field:
name: valid
description: To be set when all offline values are set.
description: >
To be set when all offline values are set and coherent. The
hardware will use them at the next start. User shouldn't
modify the offline values once this bit is set.
range: 0
x-hdl:
type: wire
......
hdl/rtl/vtu_blk.vhd
View file @ f4679007
......@@ -83,6 +83,13 @@ architecture rtl of vtu_blk is
wvalue : std_logic_vector (63 downto 0);
end record;
constant c_no_vtu_params : t_vtu_params :=
(mode => (others => '0'),
htswitchen => '0',
bvalue => (others => '0'),
htvalue => (others => '0'),
wvalue => (others => '0'));
-- VTU offline parameters.
signal params_offline : t_vtu_params;
signal valid_offline : std_logic;
......@@ -90,8 +97,8 @@ architecture rtl of vtu_blk is
signal valid_wr : std_logic;
-- VTU inline parameters (for clk_sys and clk_vtu domains)
signal params_online : t_vtu_params;
signal params_vtu : t_vtu_params;
signal params_online : t_vtu_params;
signal vtu_use_sync_as_start : std_logic;
......@@ -161,6 +168,13 @@ begin
clk_rf_n <= not clk_rf_i;
-- Synchronize start_i
-- Path: start_i (async)
-- --> start_pulse_sys (clk_sys)
-- --> start_pulse_2 (clk_sys, if ready)
-- --> vtu_start (clk_vtu)
-- --> vtu_start_d (clk_vtu, after loading the config)
-- [read by the vtu]
inst_start_isync: entity work.gc_sync_edge
generic map (
g_edge => "positive"
......@@ -216,6 +230,7 @@ begin
start_pulse_2 <= '0';
miss_ready <= '0';
miss_valid <= '0';
params_online <= c_no_vtu_params;
else
start_pulse_2 <= '0';
if start_pulse_sys = '1' or soft_start = '1' then
......@@ -227,6 +242,7 @@ begin
-- Clear miss status. Sticky version ?
miss_ready <= '0';
miss_valid <= '0';
params_online <= params_offline;
else
-- If not ready, set flags.
miss_ready <= not start_ready;
......@@ -240,7 +256,7 @@ begin
elsif valid_wr = '1' then
-- Write to VALID register from WB.
-- TODO: do not allow change of offline data if the valid bit is set.
-- TODO: detect ingored writs to offline data if the valid bit is set.
-- TODO: detect ingored writes to offline data if the valid bit is set.
valid_offline <= valid_data;
end if;
end if;
......@@ -251,11 +267,7 @@ begin
begin
if rising_edge (clk_vtu_i) then
if rst_vtu_n = '0' then
params_vtu <= (mode => (others => '0'),
htswitchen => '0',
bvalue => (others => '0'),
htvalue => (others => '0'),
wvalue => (others => '0'));
params_vtu <= c_no_vtu_params;
vtu_start_d <= '0';
else
vtu_start_d <= '0';
......@@ -269,11 +281,7 @@ begin
vtu_start_d <= '1';
else
-- Parameters are not valid -> set to 0.
params_vtu <= (mode => (others => '0'),
htswitchen => '0',
bvalue => (others => '0'),
htvalue => (others => '0'),
wvalue => (others => '0'));
params_vtu <= c_no_vtu_params;
end if;
end if;
end if;
......
hdl/testbench/vtu/tb_vtu.vhd
View file @ f4679007
......@@ -23,12 +23,38 @@ architecture arch of tb_vtu is
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
function to_string(v : std_ulogic) return character is
begin
case v is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'X' => return 'X';
when 'Z' => return 'Z';
when 'L' => return 'L';
when 'H' => return 'H';
when 'W' => return 'W';
when '-' => return '-';
end case;
end to_string;
function to_string(v : std_logic_vector) return string is
alias av : std_logic_vector(1 to v'length) is v;
variable res : string(av'range);
begin
for i in av'range loop
res (i) := to_string(av (i));
end loop;
return res;
end to_string;
begin
-- System clock, 62.5 Mhz
clk_sys <= not clk_sys after 8 ns;
rst_sys <= '1', '0' after 16 ns;
-- RF clock, ~200Mhz
-- RF clock, ~200Mhz (5ns)
-- VTU clock, ~25Mhz (40ns)
process
variable cnt : natural := 8;
begin
......@@ -56,10 +82,13 @@ begin
);
process
variable val : std_logic_vector(15 downto 0);
begin
sync <= '0';
start <= '0';
wait until rst_sys = '0';
-- Program the diag (500us)
write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_TRIGDIAG + ADDR_VTUDIAG_REGS_CONTROL, x"0000");
......@@ -69,7 +98,7 @@ begin
-- Delay between the pulses.
write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEOFFLINE, x"0000_0000_0000_0008");
-- Number of pulses.
write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE, x"0000_0000_0000_0004");
write64be_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEOFFLINE, x"0000_0000_0000_0040");
-- Windowed mode, enable.
write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGOFFLINE, x"0021");
......@@ -77,18 +106,79 @@ begin
-- Remove reset.
write16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONTROL, x"0000");
-- Check status.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
-- Set to one after reset.
assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '1' severity error;
-- Check online config is 0.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
report "config online = " & to_string(val);
assert val = x"0000" severity error;
-- Start pulse.
start <= '1';
wait for 40 ns;
start <= '0';
-- Wait until the VTU get the start pulse
for i in 1 to 7 loop
wait until rising_edge(clk_vtu);
end loop;
-- Check status.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
-- Should be 0 if close enough to the start pulse.
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGWVALUE_OFFSET) = '0' severity error;
-- Sync pulse.
wait for 200 ns;
sync <= '1';
wait for 10 ns;
sync <= '0';
-- Check ...
-- Wait until the VTU get the sync pulse.
for i in 1 to 3 loop
wait until rising_edge(clk_vtu);
end loop;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_STATUS, val);
report "status = " & to_string(val);
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '1' severity error;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '1' severity error;
-- Check online config.
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_CONFIGONLINE, val);
report "config online = " & to_string(val);
assert val = x"0020" severity error;
-- Check online registers
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 6, val);
assert val = x"0040" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 4, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 2, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 0, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEONLINE + 6, val);
assert val = x"0008" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEONLINE + 6, val);
assert val = x"0020" severity error;
wait;
end process;
end arch;
\ No newline at end of file
end arch;
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