Name change for NETs: CLK_FPGA_62M5_p and CLK_FPGA_62M5_p
For IC21 - the PLL LTC6950 - page 7.
The output names for the NETs going to the FPGA clk inputs may be misleading. The name includes a frequency. I think we should drop the frequency from the name.
- CLK_FPGA_62M5_[p,n]
- FPGA_CLKS harness as SYS_CLK_[p,n]
- CLK_SYS_62M5_[p,n] -> E17, E18 FPGA pins
If we change the operating conditions of the LTC6950 to output a different frequency, this will be confusing for later readers.
I would like to change the name to something like CLK_FPGA_SYS_[p,n].
The current clocking scheme for wr2rf is here https://ohwr.org/project/wr2rf-vme/wikis/wr2rf-fpga-clocking