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wr2rf-vme
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Replace capacitors and inductors with proper symbols in RF main sheet
#9
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
critical
hw
CLOSED
4
updated
Jun 18, 2020
wire length matching
#29
· opened
May 13, 2020
by
Tristan Gingold
Schematic done
hw
minor
CLOSED
4
updated
Jun 17, 2020
1V0 LDO current sharing scheme - questions
#26
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
question
CLOSED
8
updated
Jun 16, 2020
Trigger unit output glitches
#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
10Mhz out: from pll or from fpga ?
#41
· opened
May 20, 2020
by
Tristan Gingold
hdl
hw
question
CLOSED
4
updated
Jun 16, 2020
Missing correct symbols in rf_main sheet
#43
· opened
Jun 12, 2020
by
Mattia Rizzi
Schematic done
critical
hw
CLOSED
1
updated
Jun 12, 2020
Dielectric of ceramic capacitors in the RF path
#34
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
important
CLOSED
3
updated
Jun 10, 2020
consider using an INA240 for the OCXO current sense
#27
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
minor
CLOSED
2
updated
Jun 10, 2020
pulse shaper - questions
#21
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
hw
question
CLOSED
11
updated
Jun 10, 2020
Feature: digital potentiometer for pulse_shaper
#42
· opened
May 28, 2020
by
Mattia Rizzi
cosmetics
hw
CLOSED
1
updated
Jun 09, 2020
Is current power sequencing adequate?
#5
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
question
CLOSED
2
updated
Jun 09, 2020
Check DDS IOUPDATE signal FPGA connection
#35
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
question
CLOSED
1
updated
Jun 09, 2020
Consider serial termination on the LEN pin of the 100EP195 delay line
#36
· opened
May 13, 2020
by
Tomasz Wlostowski
Schematic done
hw
minor
CLOSED
1
updated
Jun 09, 2020
Solve wr-cores dependency
#13
· opened
Apr 27, 2020
by
Dimitris Lampridis
hdl
important
CLOSED
3
updated
Jun 09, 2020
Check terminations on shared SPI lines
#8
· opened
Apr 25, 2020
by
Dimitris Lampridis
Schematic done
hw
important
CLOSED
1
updated
Jun 09, 2020
Main RF generation
#33
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
3
updated
Jun 09, 2020
Name change for NETs: CLK_FPGA_62M5_p and CLK_FPGA_62M5_p
#14
· opened
May 06, 2020
by
John Gill
Schematic done
hdl
hw
minor
CLOSED
3
updated
Jun 08, 2020
Inconsistent pull-down for VME_RETRY_OE and VME_A_OE_N
#19
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
hw
question
CLOSED
1
updated
Jun 08, 2020
could remove VME_A_DIR and VME_LWORD_N
#18
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
cosmetics
hw
CLOSED
1
updated
Jun 08, 2020
VME connector issues
#15
· opened
May 11, 2020
by
Tom Levens
Schematic done
hw
CLOSED
1
updated
Jun 06, 2020
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