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White Rabbit Trigger Distribution
Commit b4b2b1e4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] update SPEC ADC testbench to work with the convention

parent 6118f656
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Showing with 22 additions and 12 deletions
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @ b4b2b1e4
...@@ -14,8 +14,6 @@ syn_tool = "ise" ...@@ -14,8 +14,6 @@ syn_tool = "ise"
if locals().get('fetchto', None) is None: if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies" fetchto = "../../../dependencies"
ctrls = ["bank3_64b_32b"]
files = [ files = [
"wrtd_ref_spec150t_adc.ucf", "wrtd_ref_spec150t_adc.ucf",
"buildinfo_pkg.vhd", "buildinfo_pkg.vhd",
...@@ -36,3 +34,5 @@ except: ...@@ -36,3 +34,5 @@ except:
pass pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)" syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
ctrls = ["bank3_64b_32b"]
hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
View file @ b4b2b1e4
...@@ -4,3 +4,4 @@ Makefile ...@@ -4,3 +4,4 @@ Makefile
modelsim.ini modelsim.ini
transcript* transcript*
*.wlf *.wlf
buildinfo_pkg.vhd
hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
View file @ b4b2b1e4
board = "spec" board = "spec"
sim_tool = "modelsim" sim_tool = "modelsim"
top_module = "main" sim_top = "main"
action = "simulation" action = "simulation"
target = "xilinx" target = "xilinx"
syn_device = "xc6slx150t" syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh" vcom_opt = "-93 -mixedsvvh"
fetchto = "../../../dependencies" # Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../dependencies"
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware" sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
ctrls = ["bank3_64b_32b"]
include_dirs = [ include_dirs = [
"../include", "../include",
fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm", fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
...@@ -31,3 +32,11 @@ modules = { ...@@ -31,3 +32,11 @@ modules = {
"../../top/wrtd_ref_spec150t_adc", "../../top/wrtd_ref_spec150t_adc",
], ],
} }
ctrls = ["bank3_64b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ b4b2b1e4
...@@ -291,16 +291,16 @@ module dut_env ...@@ -291,16 +291,16 @@ module dut_env
initial begin initial begin
// Skip WR SoftPLL lock // Skip WR SoftPLL lock
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.WRPC. force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111; WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0; multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0; multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0; multiplier.D3.OPMODE_dly = 0;
end // initial begin end // initial begin
......
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ b4b2b1e4
...@@ -220,7 +220,7 @@ architecture arch of wrtd_ref_spec150t_adc is ...@@ -220,7 +220,7 @@ architecture arch of wrtd_ref_spec150t_adc is
constant c_WB_SLAVE_FMC_ADC : integer := 1; constant c_WB_SLAVE_FMC_ADC : integer := 1;
constant c_WB_SLAVE_MT : integer := 2; constant c_WB_SLAVE_MT : integer := 2;
-- Convertion metadata base address -- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000"; constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout -- Primary wishbone crossbar layout
......
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