tb: add very simple fd monitor.

daee642c · Tristan Gingold · c283c9b9 · daee642c
Commit daee642c authored Aug 22, 2018 by Tristan Gingold
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Showing with 2 additions and 10 deletions

main.sv hdl/testbench/wrtd-system/main.sv +2 -10

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--- a/hdl/testbench/wrtd-system/main.sv
+++ b/hdl/testbench/wrtd-system/main.sv
@@ -159,14 +159,8 @@ module simple_fdelay_mon
   input [3:0] pulse
   );
-   task display_pulse ();
+   always@pulse begin
-      string tmp;
+      $display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", $time, len, val, pulse);
-      tmp = $sformatf("[FDEL] Pulse: len=%x, val=%x, out=%x", len, val, pulse);
-      $display (tmp);
-   endtask // display_pulse
-   always@(posedge pulse) begin
-      display_pulse();
   end
 endmodule // simple_fdelay_mon
@@ -288,7 +282,6 @@ module main;
   // WRTD receiver (Fine Delay)
   //
-/* -----\/----- EXCLUDED -----\/-----
   simple_fdelay_mon
     FDL
       (
@@ -296,7 +289,6 @@ module main;
 	.val   (fdl_val),
 	.pulse (fdl_pulse)
 	);
- -----/\----- EXCLUDED -----/\----- */
   svec_list_top #
     (