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White Rabbit Trigger Distribution
Commits
fc0b5603
Commit
fc0b5603
authored
Aug 08, 2019
by
Dimitris Lampridis
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[hdl] make SPEC testbench finish automatically when done
parent
86d87a5a
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main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
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hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
fc0b5603
...
@@ -54,6 +54,8 @@ module main;
...
@@ -54,6 +54,8 @@ module main;
const
uint64_t
MT_BASE
=
'h0002_0000
;
const
uint64_t
MT_BASE
=
'h0002_0000
;
int
sim_end
=
0
;
initial
begin
initial
begin
uint64_t
val
,
expected
;
uint64_t
val
,
expected
;
...
@@ -222,6 +224,7 @@ module main;
...
@@ -222,6 +224,7 @@ module main;
join
join
sim_end
=
1
;
end
end
...
@@ -241,7 +244,7 @@ module main;
...
@@ -241,7 +244,7 @@ module main;
$
display
(
"-------------------"
)
;
$
display
(
"-------------------"
)
;
$
display
()
;
$
display
()
;
#
5000u
s
;
wait
(
sim_end
==
1
)
;
$
display
()
;
$
display
()
;
$
display
(
"Simulation PASSED"
)
;
$
display
(
"Simulation PASSED"
)
;
...
...
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