Bug fix in command enable signal generation.

The command enable signal was not properly generated for single read cycle.

Bug fix in command enable signal generation.
The command enable signal was not properly generated for single read cycle.
cd3680a0 · Matthieu Cattin · 5bd12eae · cd3680a0
Commit cd3680a0 authored Nov 16, 2012 by Matthieu Cattin
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ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +2 -2

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--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -261,8 +261,8 @@ begin
      else
        ddr_cmd_en_d <= ddr_cmd_en;
        if (((ddr_burst_cnt = c_DDR_BURST_LENGTH) or
-             (wb_we_f_edge = '1') or
-             (wb_stb_f_edge = '1' and wb_we_d = '0')) and ddr_cmd_full_i = '0') and (ddr_cmd_en = '0')then
+             --(wb_we_f_edge = '1') or
+             (wb_stb_f_edge = '1' and wb_cyc_d = '1')) and ddr_cmd_full_i = '0') and (ddr_cmd_en = '0')then
          ddr_cmd_en <= '1';            -- might have problem if burst_cnt = BURST_LENGTH for more than 2 clk cycles
        else
          ddr_cmd_en <= '0';