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Commit 09d84b4d authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : basic MIK Kicker pulse generator block finished. Some optimizations must be done. 

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/src_MIK/MIK_detection.vhdl
	modified:   fpga/sources/src_MIK/MIK_top.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/top.vhdl
	modified:   fpga/sources/type_lib.vhdl
parent f379b568
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Showing with 112 additions and 62 deletions
fpga/sources/outputmux.vhdl
View file @ 09d84b4d
......@@ -5,6 +5,7 @@
-- Description : Output multiplexer
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-1-1-1 : MIK pulse generator
-- 0-0-0-1-1-0 : clock padding
-- 0-0-0-1-0-1 : LINAC synchonized interlock
-- 0-0-0-1-0-0 : frequency divider
......@@ -16,7 +17,7 @@
-- File : outputmux.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : December 01, 2014
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -95,6 +96,10 @@ entity outputMux is
p_test_outTTL : in std_logic_vector (4 downto 0);
p_test_outPECL : in std_logic_vector (4 downto 0);
p_test_LED : in std_logic_vector (1 downto 0);
-- Duplication block
p_MIK_outTTL : in std_logic_vector (4 downto 0);
p_MIK_outPECL : in std_logic_vector (4 downto 0);
p_MIK_LED : in std_logic_vector (1 downto 0);
-- Mux block
p_mux_SWsel : in std_logic_vector (5 downto 0);
p_mux_outTTL : out std_logic_vector (4 downto 0);
......@@ -134,6 +139,7 @@ architecture rtl_outputMux of outputMux is
p_freqDIV_outTTL when "000100",
p_linacSYNCLOCK_outTTL when "000101",
p_clkPADDING_outTTL when "000110",
p_MIK_outTTL when "000111",
p_test_outTTL when OTHERS;
-- LVPECL ouuputs selection
......@@ -146,6 +152,7 @@ architecture rtl_outputMux of outputMux is
p_freqDIV_outPECL when "000100",
p_linacSYNCLOCK_outPECL when "000101",
p_clkPADDING_outPECL when "000110",
p_MIK_outPECL when "000111",
p_test_outPECL when OTHERS;
-- LEDs outputs selection
......@@ -158,6 +165,7 @@ architecture rtl_outputMux of outputMux is
p_freqDIV_LED when "000100",
p_linacSYNCLOCK_LED when "000101",
p_clkPADDING_LED when "000110",
p_MIK_LED when "000111",
p_test_LED when OTHERS;
------------------------------------------------------------------------------
......
fpga/sources/src_MIK/MIK_detection.vhdl
View file @ 09d84b4d
......@@ -7,7 +7,7 @@
-- File : MIK_detection.vhd
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 28, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -39,6 +39,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.registers_init.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
......@@ -67,6 +70,8 @@ architecture rtl_MIK_detection of MIK_detection is
-- s_fallingEdge : std_logic;
signal s_cntPulseWidth : unsigned (31 downto 0);
signal s_cntPulseWidthMax : unsigned (31 downto 0);
signal s_start : std_logic;
signal s_end : std_logic;
signal s_rstCNT : std_logic;
signal s_delayed : std_logic_vector (4 downto 1);
......@@ -84,7 +89,7 @@ architecture rtl_MIK_detection of MIK_detection is
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk60MHz)) then
s_resync <= s_resync (1 downto 0) & p_inTTL(0);
s_resync <= s_resync (1 downto 0) & p_in;
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
end if;
......@@ -117,11 +122,12 @@ architecture rtl_MIK_detection of MIK_detection is
s_end <= '1';
p_out <= '0';
else
s_cntPulseWidth <= s_cntGateWidth + 1;
s_cntPulseWidth <= s_cntPulseWidth + 1;
s_end <= '0';
p_out <= '1';
end if;
end if;
end process;
-- Latch from the register the pulse width
process (p_reset, p_clk60MHz)
......@@ -130,7 +136,7 @@ architecture rtl_MIK_detection of MIK_detection is
s_cntPulseWidthMax <= unsigned (c_wRegister_init(16));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(1) = '1') then
if (p_csw = '1') then
s_cntPulseWidthMax <= unsigned (p_pulseWidth);
s_rstCNT <= '1';
else
......
fpga/sources/src_MIK/MIK_top.vhdl
View file @ 09d84b4d
......@@ -11,7 +11,7 @@
-- File : MIK_top.vhdl
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 28, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -87,10 +87,10 @@ architecture rtl_MIK_top of MIK_top is
port map (
p_reset => p_MIK_reset,
p_clk60MHz => p_MIK_clk60MHz,
p_in => p_MIK_inTTL(0), -- TTL in
p_in => p_MIK_inTTL, -- TTL in
p_pulseWidth => p_MIK_pulseWidth,
p_csw => p_MIK_csw(0),
p_out => s_outPulse -- out
p_out => s_outPulse -- out
);
-- Signal duplication block
......
fpga/sources/src_cPCI/cPCI_hermes.vhdl
View file @ 09d84b4d
......@@ -22,7 +22,7 @@
-- File : cPCI_hermes.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : December 06, 2013
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -88,9 +88,9 @@ entity cPCI_hermes is
p_config_reg : in std_logic_vector (31 downto 0); -- configurarion register
p_status_reg : in std_logic_vector (29 downto 0); -- bit 31 & 30 are reserved for access error
p_wRegister : out register_array;
p_wRegister_init : in register_array;
p_rRegister : in register_array;
p_wRegister : out cpci_register_array;
p_wRegister_init : in cpci_register_array;
p_rRegister : in cpci_register_array;
p_CSW : out std_logic_vector (15 downto 0); -- chip select of internal write transfert
p_CSR : out std_logic_vector (15 downto 0); -- chip select of internal read transfert
......
fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
View file @ 09d84b4d
......@@ -7,7 +7,7 @@
-- File : cPCI_hermes_registers.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : December 04, 2013
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -60,7 +60,7 @@ package cPCI_hermes_registers is
constant c_add_cmd_reg : std_logic_vector (9 downto 2) := "00000101"; -- commands register
constant c_add_foo_reg : std_logic_vector (9 downto 2) := "00010100"; -- foo register, not used
constant c_add_register : add_register_array := (
constant c_add_register : add_cpci_register_array := (
"00000110", -- register 0
"00000111", -- register 1
"00001000", -- register 2
......@@ -98,7 +98,7 @@ package cPCI_hermes_registers is
-- wRegister 11 ; s_CSW = "001000000000000"
-- wRegister 12 ; s_CSW = "010000000000000"
-- wRegister 13 ; s_CSW = "100000000000000"
signal s_wRegister : register_array;
signal s_wRegister : cpci_register_array;
-- Read registers
-- rRegister 0 ; CSR = "000000000000001"
......@@ -115,7 +115,7 @@ package cPCI_hermes_registers is
-- rRegister 11 ; CSR = "000100000000000"
-- rRegister 12 ; CSR = "001000000000000"
-- rRegister 13 ; CSR = "010000000000000"
signal s_rRegister : register_array;
signal s_rRegister : cpci_register_array;
end package cPCI_hermes_registers;
......
fpga/sources/src_cPCI/cPCI_registerMux.vhdl
View file @ 09d84b4d
......@@ -16,7 +16,7 @@
-- File : cPCI_registerMux.vhdl
-- Revision : x.x.x
-- Created : November 17, 2013
-- Updated : April 28, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -58,10 +58,10 @@ use work.type_lib.all;
entity cPCI_registerMux is
port (
-- cPCI registers
p_wRegister : in register_array;
p_wRegister_init : out register_array;
p_wRegister : in cpci_register_array;
p_wRegister_init : out cpci_register_array;
p_rRegister : out register_array;
p_rRegister : out cpci_register_array;
-- Mux in / out
p_mux_wRegister : out register_array;
......@@ -173,48 +173,61 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_wRegister(1) when "000100",
X"00000000" when OTHERS;
-- MIK pulse generator
with p_mux_SWsel select
p_mux_wRegister(16) <=
p_wRegister(0) when "000000",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(17) <=
p_wRegister(1) when "000000",
X"00000000" when OTHERS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Write registers init values mux
with p_mux_SWsel select
p_wRegister_init(0) <=
c_wRegister_init(0) when "000000",
c_wRegister_init(2) when "000001",
c_wRegister_init(6) when "000010",
c_wRegister_init(8) when "000011",
c_wRegister_init(14) when "000100",
c_wRegister_init(0) when "000000", -- diplication
c_wRegister_init(2) when "000001", -- top-up gating
c_wRegister_init(6) when "000010", -- LINAC SPM multipulse
c_wRegister_init(8) when "000011", -- LINAC monitor
c_wRegister_init(14) when "000100", -- Frequency divider
c_wRegister_init(16) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(1) <=
c_wRegister_init(1) when "000000",
c_wRegister_init(3) when "000001",
c_wRegister_init(7) when "000010",
c_wRegister_init(9) when "000011",
c_wRegister_init(15) when "000100",
c_wRegister_init(1) when "000000", -- diplication
c_wRegister_init(3) when "000001", -- top-up gating
c_wRegister_init(7) when "000010", -- LINAC SPM multipulse
c_wRegister_init(9) when "000011", -- LINAC monitor
c_wRegister_init(15) when "000100", -- Frequency divider
c_wRegister_init(17) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(2) <=
c_wRegister_init(4) when "000001",
c_wRegister_init(10) when "000011",
c_wRegister_init(4) when "000001", -- top-up gating
c_wRegister_init(10) when "000011", -- LINAC monitor
c_wRegister_init(18) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(3) <=
c_wRegister_init(5) when "000001",
c_wRegister_init(11) when "000011",
c_wRegister_init(5) when "000001", -- top-up gating
c_wRegister_init(11) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(4) <=
c_wRegister_init(12) when "000011",
c_wRegister_init(12) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(5) <=
c_wRegister_init(13) when "000011",
c_wRegister_init(13) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
p_wRegister_init(6) <= X"00000000";
......@@ -232,42 +245,45 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
-- Read mux
with p_mux_SWsel select
p_rRegister(0) <=
p_mux_rRegister(0) when "000000",
p_mux_rRegister(2) when "000001",
p_mux_rRegister(6) when "000010",
p_mux_rRegister(8) when "000011",
p_mux_rRegister(14) when "000100",
p_mux_rRegister(0) when "000000", -- diplication
p_mux_rRegister(2) when "000001", -- top-up gating
p_mux_rRegister(6) when "000010", -- LINAC SPM multipulse
p_mux_rRegister(8) when "000011", -- LINAC monitor
p_mux_rRegister(14) when "000100", -- Frequency divide
p_mux_rRegister(16) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(1) <=
p_mux_rRegister(1) when "000000",
p_mux_rRegister(3) when "000001",
p_mux_rRegister(7) when "000010",
p_mux_rRegister(9) when "000011",
p_mux_rRegister(15) when "000100",
p_mux_rRegister(1) when "000000", -- diplication
p_mux_rRegister(3) when "000001", -- top-up gating
p_mux_rRegister(7) when "000010", -- LINAC SPM multipulse
p_mux_rRegister(9) when "000011", -- LINAC monitor
p_mux_rRegister(15) when "000100", -- Frequency divide
p_mux_rRegister(17) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(2) <=
p_mux_rRegister(4) when "000001",
p_mux_rRegister(10) when "000011",
p_mux_rRegister(4) when "000001", -- top-up gating
p_mux_rRegister(10) when "000011", -- LINAC monitor
p_mux_rRegister(18) when "000111", -- MIK
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(3) <=
p_mux_rRegister(5) when "000001",
p_mux_rRegister(11) when "000011",
p_mux_rRegister(5) when "000001", -- top-up gating
p_mux_rRegister(11) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(4) <=
p_mux_rRegister(12) when "000011",
p_mux_rRegister(12) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(5) <=
p_mux_rRegister(13) when "000011",
p_mux_rRegister(13) when "000011", -- LINAC monitor
X"00000000" when OTHERS;
p_rRegister(6) <= X"00000000";
......@@ -358,7 +374,21 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_csw(2) when "000100",
'0' when OTHERS;
p_csw(20 downto 17) <= (OTHERS => '0');
-- MIK pulse generator write stobe mux
with p_mux_SWsel select
p_csw(17) <=
p_mux_csw(1) when "000111",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(18) <=
p_mux_csw(2) when "000111",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(19) <=
p_mux_csw(3) when "000111",
'0' when OTHERS;
p_csw(20) <= '0';
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
fpga/sources/src_cPCI/cPCI_statusManager.vhdl
View file @ 09d84b4d
......@@ -9,7 +9,7 @@
-- File : cPCI_statusManager.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : December 01, 2014
-- Updated : April 29, 2015
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -49,7 +49,7 @@ use work.registers_init.all;
-------------------------------------------------------------------------------
entity cPCI_statusManager is
port (
p_inStates : in std_logic_vector (10 downto 0);
p_inStates : in std_logic_vector (11 downto 0);
p_status : out std_logic_vector (29 downto 0);
p_cfgSW : in std_logic_vector (5 downto 0);
p_clk60MHz : in std_logic;
......@@ -91,6 +91,7 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
when "000011" => s_status <= "0000000" & p_inStates(8 downto 6);
when "000100" => s_status <= "000000000" & p_inStates(9);
when "000101" => s_status <= "000000000" & p_inStates(10);
when "000111" => s_status <= "000000000" & p_inStates(11);
when others => s_status <= "0000000000";
end case;
end if;
......
fpga/sources/top.vhdl
View file @ 09d84b4d
......@@ -7,7 +7,7 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : April 28, 2015
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -150,10 +150,10 @@ architecture rtl_top of top is
-- synchro pulse is signaled
signal s_MIKpulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_wRegister : register_array;
signal s_wRegister_init : register_array;
signal s_wRegister : cpci_register_array;
signal s_wRegister_init : cpci_register_array;
signal s_rRegister : register_array;
signal s_rRegister : cpci_register_array;
signal s_wRegister_foo0 : std_logic_vector (31 downto 0);
signal s_wRegister_foo6 : std_logic_vector (31 downto 0);
......@@ -651,6 +651,10 @@ architecture rtl_top of top is
p_clkPADDING_outTTL => s_clkPaddingOutTTL,
p_clkPADDING_outPECL => s_clkPaddingOutPECL,
p_clkPADDING_LED => s_clkPaddingLED,
-- MIK pulse generator
p_MIK_outTTL => s_MIKOutTTL,
p_MIK_outPECL => s_MIKOutPECL,
p_MIK_LED => s_MIKLED,
-- Mux block mux outputs
p_mux_SWsel => pin_SW,
p_mux_outTTL => pin_outTTL,
......
fpga/sources/type_lib.vhdl
View file @ 09d84b4d
......@@ -7,7 +7,7 @@
-- File : type_lib.vhdl
-- Revision : x.x.x
-- Created : Decemeber 04, 2013
-- Updated : February 03, 2014
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -44,8 +44,9 @@ use ieee.numeric_std.all;
--------------------------------------------------------------------------------
package type_lib is
type register_array is array (0 to 15) of std_logic_vector (31 downto 0);
type add_register_array is array (0 to 13) of std_logic_vector (9 downto 2);
type register_array is array (0 to 18) of std_logic_vector (31 downto 0);
type cpci_register_array is array (0 to 13) of std_logic_vector (31 downto 0);
type add_cpci_register_array is array (0 to 13) of std_logic_vector (9 downto 2);
end package type_lib;
......
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