VHDL : added clock padding for CRISTAL beamline laser

On branch development modified: fpga/sources/outputmux.vhdl modified: fpga/sources/registers_init.vhdl new file: fpga/sources/src_clkpadding/clkpadding_config.txt new file: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/src_topup/topup_top.vhdl modified: fpga/sources/top.vhdl

VHDL : added clock padding for CRISTAL beamline laser
On branch development modified: fpga/sources/outputmux.vhdl modified: fpga/sources/registers_init.vhdl new file: fpga/sources/src_clkpadding/clkpadding_config.txt new file: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/src_topup/topup_top.vhdl modified: fpga/sources/top.vhdl
2d45d219 · Jean-Paul Ricaud · 618e1548 · 2d45d219 · 2d45d219 · 2d45d219
Commit 2d45d219 authored Sep 22, 2014 by Jean-Paul Ricaud
6 changed files
--- a/fpga/sources/outputmux.vhdl
+++ b/fpga/sources/outputmux.vhdl
@@ -5,6 +5,7 @@
 -- Description : Output multiplexer
 --  SW 5-4-3-2-1-0
 --     1-1-1-1-1-1 : board test
+--     0-0-0-1-0-1 : clock padding
 --     0-0-0-1-0-0 : frequency divider
 --     0-0-0-0-1-1 : LINAC monitoring
 --     0-0-0-0-1-0 : LINAC multipulse
@@ -14,7 +15,7 @@
 -- File     : outputmux.vhdl
 -- Revision : x.x.x
 -- Created  : October 26, 2012
-- Updated  : February 03, 2013
+-- Updated  : September 19, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -43,6 +44,8 @@
 --     * Added LINAC monitoring function
 --   Version 1.6.1 ; February 03 2014 ; Jean-Paul Ricaud
 --     * Added frequency divider block for slicing DG
+--   Version 1.8.0 ; September 19 2014 ; Jean-Paul Ricaud
+--     * Added clock padding for CRISTAL beamline laser syncgrinization
 --
 --------------------------------------------------------------------------------

@@ -75,6 +78,10 @@ entity outputMux is
    p_freqDIV_outTTL   : in std_logic_vector (4 downto 0);
    p_freqDIV_outPECL  : in std_logic_vector (4 downto 0);
    p_freqDIV_LED      : in std_logic_vector (1 downto 0);
+    -- clock padding block
+    p_clkPADDING_outTTL  : in std_logic_vector (4 downto 0);
+    p_clkPADDING_outPECL : in std_logic_vector (4 downto 0);
+    p_clkPADDING_LED     : in std_logic_vector (1 downto 0);
    -- Test block
    p_test_outTTL      : in std_logic_vector (4 downto 0);
    p_test_outPECL     : in std_logic_vector (4 downto 0);
@@ -111,32 +118,35 @@ architecture rtl_outputMux of outputMux is
  -- TTL ouuputs selection
  with p_mux_SWsel select
    p_mux_outTTL <=
-      p_dup_outTTL      when "000000",
-      p_topUp_outTTL    when "000001",
-      p_linacMP_outTTL  when "000010",
-      p_linacMON_outTTL when "000011",
-      p_freqDIV_outTTL  when "000100",
-      p_test_outTTL     when OTHERS;
+      p_dup_outTTL        when "000000",
+      p_topUp_outTTL      when "000001",
+      p_linacMP_outTTL    when "000010",
+      p_linacMON_outTTL   when "000011",
+      p_freqDIV_outTTL    when "000100",
+      p_clkPADDING_outTTL when "000101",
+      p_test_outTTL       when OTHERS;

  -- LVPECL ouuputs selection
  with p_mux_SWsel select
    p_mux_outPECL <=
-      p_dup_outPECL      when "000000",
-      p_topUp_outPECL    when "000001",
-      p_linacMP_outPECL  when "000010",
-      p_linacMON_outPECL when "000011",
-      p_freqDIV_outPECL  when "000100",
-      p_test_outPECL     when OTHERS;
+      p_dup_outPECL        when "000000",
+      p_topUp_outPECL      when "000001",
+      p_linacMP_outPECL    when "000010",
+      p_linacMON_outPECL   when "000011",
+      p_freqDIV_outPECL    when "000100",
+      p_clkPADDING_outPECL when "000101",
+      p_test_outPECL       when OTHERS;

  -- LEDs outputs selection
  with p_mux_SWsel select
    p_mux_outLED <=
-      p_dup_LED      when "000000",
-      p_topUp_LED    when "000001",
-      p_linacMP_LED  when "000010",
-      p_linacMON_LED when "000011",
-      p_freqDIV_LED  when "000100",
-      p_test_LED     when OTHERS;
+      p_dup_LED        when "000000",
+      p_topUp_LED      when "000001",
+      p_linacMP_LED    when "000010",
+      p_linacMON_LED   when "000011",
+      p_freqDIV_LED    when "000100",
+      p_clkPADDING_LED when "000101",
+      p_test_LED       when OTHERS;

  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------

--- a/fpga/sources/registers_init.vhdl
+++ b/fpga/sources/registers_init.vhdl
@@ -9,7 +9,7 @@
 -- File     : registers_init.vhdl
 -- Revision : x.x.x
 -- Created  : March 06, 2013
-- Updated  : February 03, 2014
+-- Updated  : September 19, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -78,7 +78,7 @@ package registers_init is

  -- Read registers
  constant c_board_id     : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
-  constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000A1"; -- firmware's version
+  constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000B4"; -- firmware's version

 end package registers_init;


--- a/fpga/sources/src_clkpadding/clkpadding_config.txt
+++ b/fpga/sources/src_clkpadding/clkpadding_config.txt
+------------------------------------------------------------------------------
+-- Title   : Configuration of TimEX3
+-- Project : TimEX3
+-------------------------------------------------------------------------------
+-- Description : Differents configuration of the TimEX3
+-------------------------------------------------------------------------------
+-- File     : clkpadding_config.txt
+-- Revision : x.x.x
+-- Created  : September 19, 2014
+-- Updated  : September 19, 2014
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - 2014 Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+===============================================================================
+Configuration : duplication 1 input to 4 outputs
+
+SW : 5-4-3-2-1-0
+     0-0-0-1-0-1
+
+IO0 : input  - monitored clock signal
+IO1 : output - storage ring clock signal
+IO2 : output - padded clock signal
+IO3 : output - padded clock signal
+IO4 : output - padded clock signal
+
+Green LED on = OK
+Red LED on   = missing clock on the input
+
+R3, R16, R29, R30, R31 => Qty = 1
+R6, R28, R17, R18, R19 => Qty = 0
+===============================================================================
+
--- a/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+++ b/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+--------------------------------------------------------------------------------
+-- Title   : Top - clock padding function
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : generate a 1 kHz clock on the output whenever the input 1 kHz
+--               clock is missing on the input.
+--               It is used by Cristal laser synchro system to avoid gaps in the
+--               1 kHz clock when changing delays
+--------------------------------------------------------------------------------
+-- File     : clkpadding_top.vhdl
+-- Revision : x.x.x
+-- Created  : July 19, 2014
+-- Updated  : Septembre 19, 2014
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - 2014 Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the Lesser GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity clkPADDING_top is
+  port (
+    p_clkPADDING_clk_mon : in  std_logic; -- monitored clock
+    p_clkPADDING_clk_sr  : in  std_logic; -- storage ring clock
+    p_clkPADDING_reset   : in  std_logic; -- global reset
+    p_clkPADDING_outTTL  : out std_logic_vector (4 downto 0); -- TTL outputs  -- output clock
+    p_clkPADDING_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
+    p_clkPADDING_LED     : out std_logic_vector (1 downto 0)
+  );
+end entity clkPADDING_top;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture rtl_clkPADDING_top of clkPADDING_top is
+
+  ------------------------------------------------------------------------------
+  -- constant
+  ------------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------------
+  -- signal
+  ------------------------------------------------------------------------------
+  signal s_cnt1 : unsigned (10 downto 0); -- counter
+  signal s_cnt2 : unsigned (10 downto 0); -- counter
+
+  signal s_start         : std_logic;
+  signal s_underProgress : std_logic;
+  signal s_clkPadding    : std_logic;
+  signal s_reset         : std_logic;
+
+  ------------------------------------------------------------------------------
+  --------------------------------- Main ---------------------------------------
+  ------------------------------------------------------------------------------
+  begin
+
+  -- Detection of a gap in the input clock
+  process (s_reset, p_clkPADDING_clk_sr)
+  begin
+    if (s_reset = '1') then
+      s_cnt1  <= (OTHERS => '0');
+      s_start <= '0';
+    elsif (rising_edge(p_clkPADDING_clk_sr)) then
+      if (s_cnt1 = X"1A7") then
+        s_start <= '1';
+        s_cnt1  <= s_cnt1;
+      else
+        s_cnt1  <= s_cnt1 + 1;
+      end if;
+    end if;
+  end process;
+
+  -- Generation of a padding clock if a gap is detected
+  -- in the input clock
+  process (p_clkPADDING_reset, p_clkPADDING_clk_sr)
+  begin
+    if (p_clkPADDING_reset = '1') then
+      s_cnt2          <= (OTHERS => '0');
+      s_underProgress <= '0';
+      s_clkPadding    <= p_clkPADDING_clk_mon;
+    elsif (rising_edge(p_clkPADDING_clk_sr)) then
+      if ((s_start = '1') or (s_underProgress = '1')) then
+        s_cnt2  <= s_cnt2 + 1;
+        if (s_cnt2 < X"2C1") then
+          s_underProgress <= '1';
+          s_clkPadding    <= '1';
+        elsif (s_cnt2 < X"32D") then
+          s_underProgress <= '1';
+          s_clkPadding    <= '0';
+        else
+          s_cnt2          <= (OTHERS => '0');
+          s_underProgress <= '0';
+          s_clkPadding    <= '0';
+        end if;
+      else
+        s_cnt2          <= (OTHERS => '0');
+        s_underProgress <= '0';
+        s_clkPadding    <= p_clkPADDING_clk_mon;
+      end if;
+    end if;
+  end process;
+
+  ------------------------------------------------------------------------------
+  ------------------------------------------------------------------------------
+  s_reset <= p_clkPADDING_reset or s_clkPadding;
+
+  p_clkPADDING_outTTL(0) <= '0'; -- not used ; is configured as input
+  p_clkPADDING_outTTL(1) <= '0'; -- not used ; is configured as input
+  p_clkPADDING_outTTL(2) <= s_clkPadding;
+  p_clkPADDING_outTTL(3) <= s_clkPadding;
+  p_clkPADDING_outTTL(4) <= s_clkPadding;
+
+  p_clkPADDING_outPECL(4 downto 0) <= "00000";
+
+  p_clkPADDING_led(0) <= s_underProgress;
+  p_clkPADDING_led(1) <= '1'; -- green LED ON
+
+end architecture rtl_clkPADDING_top;
--- a/fpga/sources/src_topup/topup_top.vhdl
+++ b/fpga/sources/src_topup/topup_top.vhdl
@@ -7,7 +7,7 @@
 --               output(3) : negative beam lost
 --               output(4) : negative (beam lost + gating) window
 --------------------------------------------------------------------------------
-- File     : top_topup.vhdl
+-- File     : topup_top.vhdl
 -- Revision : x.x.x
 -- Created  : October 26, 2012
 -- Updated  : November 06, 2013

--- a/fpga/sources/top.vhdl
+++ b/fpga/sources/top.vhdl
@@ -7,7 +7,7 @@
 -- File     : top.vhd
 -- Revision : x.x.x
 -- Created  : October 26, 2012
-- Updated  : February 03, 2014
+-- Updated  : September 19, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -47,6 +47,8 @@
 --       of level
 --   Version 1.6.1 ; February 03 2014 ; Jean-Paul Ricaud
 --     * Added frequency divider block for slicing DG
+--   Version 1.8.0 ; September 19 2014 ; Jean-Paul Ricaud
+--     * Added clock padding for CRISTAL beamline laser syncgrinization
 --
 --------------------------------------------------------------------------------

@@ -188,6 +190,11 @@ architecture rtl_top of top is
  signal s_freqDivOutPECL : std_logic_vector (4 downto 0);
  signal s_freqDivLED     : std_logic_vector (1 downto 0);

+  -- Clock padding signals
+  signal s_clkPaddingOutTTL  : std_logic_vector (4 downto 0);
+  signal s_clkPaddingOutPECL : std_logic_vector (4 downto 0);
+  signal s_clkPaddingLED     : std_logic_vector (1 downto 0);
+
  ------------------------------------------------------------------------------
  -- Attributes
  ------------------------------------------------------------------------------
@@ -510,6 +517,17 @@ architecture rtl_top of top is
      p_freqDIV_LED               => s_freqDivLED
    );

+  -- Clock padding block
+  clkPADDING : entity work.clkPADDING_top (rtl_clkPADDING_top)
+    port map (
+      p_clkPADDING_clk_mon         => pin_inTTL(0),
+      p_clkPADDING_clk_sr          => pin_inTTL(1),
+      p_clkPADDING_reset           => s_reset,
+      p_clkPADDING_outTTL          => s_clkPaddingOutTTL,
+      p_clkPADDING_outPECL         => s_clkPaddingOutPECL,
+      p_clkPADDING_LED             => s_clkPaddingLED
+    );
+
  -- Test
  test : entity work.test_top (rtl_test_top)
    port map (
@@ -547,7 +565,11 @@ architecture rtl_top of top is
      p_freqDIV_outTTL  => s_freqDivOutTTL,
      p_freqDIV_outPECL => s_freqDivOutPECL,
      p_freqDIV_LED     => s_freqDivLED,
-       -- Mux block outputs
+      -- Clock padding block inputs
+      p_clkPADDING_outTTL  => s_clkPaddingOutTTL,
+      p_clkPADDING_outPECL => s_clkPaddingOutPECL,
+      p_clkPADDING_LED     => s_clkPaddingLED,
+      -- Mux block outputs
      p_mux_SWsel       => pin_SW,
      p_mux_outTTL      => pin_outTTL,
      p_mux_outPECL     => pin_outPECL,