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Commit 2e1b5d75 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : pre charge event is copied to the output 2 

 On branch development

	modified:   CAD/TimEX3_linacSyncLock-FP.dwg
	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
parent edb232e3
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fpga/TimEX3/TimEX3_eeprom.mcs
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fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt
View file @ 2e1b5d75
......@@ -7,7 +7,7 @@
-- File : linacSYNCLOCK_config.txt
-- Revision : x.x.x
-- Created : July 10, 2013
-- Updated : November 28, 2014
-- Updated : December 15, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -37,7 +37,7 @@
===============================================================================
Configuration : synchronization of the interlock of the LINAC synchronization
signals ; 1 inputs - 4 outputs
signals ; 2 inputs - 3 outputs
SW : 5-4-3-2-1-0
0-0-0-1-0-1
......@@ -45,11 +45,11 @@ SW : 5-4-3-2-1-0
IO0 : input - interlock signal
IO1 : input - precharge event
IO2 : output - synchronized interlock signal
IO3 : output - synchronized interlock signal
IO3 : output - precharge event
IO4 : output - +5V
Green LED on = OK
Red LED on = simultaneous SPM and LPM triggers detected
Red LED on = inhibition ON
R3, R16, R29, R30, R31 => Qty = 1
R6, R28, R17, R18, R19 => Qty = 0
......
fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
View file @ 2e1b5d75
......@@ -6,11 +6,45 @@
-- signal is freezed in its current state during a defined delay
-- to avoid troncating the injection signal.
--
-- pre-charge injection extraction
-- ___ ___ ___
-- ____| |___________________| |___________________| |_________________
-- :
-- ==========================XXXXXXXXXXXX====================================
-- :<------------------->:<-------->:<-----------------------------------
-- : t start : t freeze : wait next pre-charge
-- : interlock monitored : freezed : interlock monitored
--
--
-- LPM
-- ___
-- ___________________________| |__________________________________________
-- -------------------------->:
-- 0.131841163386 s :
-- : SPM
-- : ___
-- _______________________________________________| |______________________
-- :<----------------->:
-- : 82.295 s :
-- : :
-- =========================XXXXXXXXXXXXXXXXXXXXXXXXXXXX=====================
-- ------------------------>:<------------------------>:
-- t start : t freeze :
-- 0.131821633861 s : 120 s :
-- = X"78AFB2" / 60MHz : = "1C20" / 60MHz :
--
--
-- Local LPM delay = 5459333 steps = 0.0310016 s ; event = 2
-- Local SPM delay = 5473825 steps = 0.0310839 s ; event = 2
-- Local PRE delay = 0 steps ; event = 1
-- CENTRAL inj delay = 193019 steps = 0.10084 s
-- CENTRAL pre delay = 0 steps
--
--------------------------------------------------------------------------------
-- File : linacSYNCLOCK_synchroInterlock.vhdl
-- Revision : x.x.x
-- Created : November 28, 2014
-- Updated : December 02, 2014
-- Updated : December 12, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -66,8 +100,8 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant c_cntmax_precharge : unsigned (23 downto 0) := X"12380F";
constant c_cntmax_freeze : unsigned (15 downto 0) := X"176E";
constant c_cntmax_precharge : unsigned (23 downto 0) := X"78AFB1";
constant c_cntmax_freeze : unsigned (15 downto 0) := X"1C1E"; -- 120 s window
------------------------------------------------------------------------------
-- signal
......
fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
View file @ 2e1b5d75
......@@ -11,10 +11,33 @@
-- ___ ___ ___
-- ____| |___________________| |___________________| |_________________
-- :
-- ==========================XXXXXXXXXXX=====================================
-- :<------------------->:<------->:<------------------------------------
-- : start countdown : t freez : wait next pre-charge
-- : interlock monitored : freezed : interlock monitored
-- ==========================XXXXXXXXXXXX====================================
-- :<------------------->:<-------->:<-----------------------------------
-- : t start : t freeze : wait next pre-charge
-- : interlock monitored : freezed e: interlock monitored
--
--
-- LPM
-- ___
-- ___________________________| |__________________________________________
-- -------------------------->:
-- 0.131841163386 s :
-- : SPM
-- : ___
-- _______________________________________________| |______________________
-- :<----------------->:
-- : 82.295 s :
-- : :
-- =========================XXXXXXXXXXXXXXXXXXXXXXXXXXXX=====================
-- ------------------------>:<------------------------>:
-- t start : t freeze :
-- 0.131821633861 s : 120 s :
--
-- Local LPM delay = 5459333 steps = 0.0310016 s ; event = 2
-- Local SPM delay = 5473825 steps = 0.0310839 s ; event = 2
-- Local PRE delay = 0 steps ; event = 1
-- CENTRAL inj delay = 193019 steps = 0.10084 s
-- CENTRAL pre delay = 0 steps
--
-- p_linacSYNCLOCK_inTTL(0) = pre-charge event
-- p_linacSYNCLOCK_inTTL(1) = interlock signal
......@@ -22,7 +45,7 @@
-- File : linacSYNCLOCK_top.vhdl
-- Revision : x.x.x
-- Created : November 28, 2014
-- Updated : December 02, 2014
-- Updated : December 15, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -132,7 +155,7 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
p_linacSYNCLOCK_outTTL (0) <= '0'; -- not used ; is configured as input
p_linacSYNCLOCK_outTTL (1) <= '0'; -- not used ; is configured as input
p_linacSYNCLOCK_outTTL (2) <= s_linacSYNCLOCK_synchro_interlock; -- synchronized interlock signal
p_linacSYNCLOCK_outTTL (3) <= s_linacSYNCLOCK_synchro_interlock; -- synchronized interlock signal
p_linacSYNCLOCK_outTTL (3) <= p_linacSYNCLOCK_inTTL(1); -- pre charge event
p_linacSYNCLOCK_outTTL (4) <= '1'; -- forced to 1 for test purpose
p_linacSYNCLOCK_outPECL (4 downto 0) <= "00000";
......
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