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Commit 686fe9ce authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : Monitoring now reacts on rising edge of the signal instead of high level 

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_leds.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_monitoring.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_monitoring.vhdl
	modified:   fpga/sources/top.vhdl
parent 8ee6950d
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fpga/TimEX3/TimEX3_eeprom.mcs
View file @ 686fe9ce
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fpga/sources/src_duplication/dup_leds.vhdl
View file @ 686fe9ce
......@@ -17,7 +17,7 @@
-- File : dup_leds.vhdl
-- Revision : x.x.x
-- Created : November 07, 2012
-- Updated : March 13, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -42,7 +42,9 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication red LED now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -87,6 +89,10 @@ architecture rtl_dup_leds of dup_leds is
signal s_greenLedON : std_logic;
signal s_blink : std_logic;
signal s_rstCNT : std_logic; -- reset the conter after a software delay update
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -125,9 +131,31 @@ architecture rtl_dup_leds of dup_leds is
-- Red LED
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after n mn.
process (p_reset, p_inTTL, s_rstCNT, p_clk1kHz)
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, s_rstCNT, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
if ((s_stop = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
s_cnt2 <= (OTHERS => '0');
p_led(0) <= '0'; -- red LED OFF
elsif (rising_edge(p_clk1kHz)) then
......
fpga/sources/src_duplication/dup_monitoring.vhdl
View file @ 686fe9ce
......@@ -9,7 +9,7 @@
-- File : dup_monitoring.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : March 11, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -34,7 +34,9 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication monitoring now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -67,16 +69,42 @@ architecture rtl_dup_monitoring of dup_monitoring is
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt : unsigned (31 downto 0); -- counter
signal s_cnt : unsigned (31 downto 0); -- counter
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
process (p_reset, p_inTTL, p_clk1kHz)
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1')) then
if ((s_stop = '1') or (p_reset = '1')) then
s_cnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_cnt < s_cntmax) then
......
fpga/sources/src_linacMON/linacMON_leds.vhdl
View file @ 686fe9ce
......@@ -17,7 +17,7 @@
-- File : linacMON_leds.vhdl
-- Revision : x.x.x
-- Created : July 09, 2013
-- Updated : July 10, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -42,7 +42,10 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Modifications :
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Monitoring now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -93,6 +96,10 @@ architecture rtl_linacMON_leds of linacMON_leds is
signal s_blink : std_logic;
signal s_rstCNT2 : std_logic; -- reset the conter after a software SPM delay update
signal s_rstCNT3 : std_logic; -- reset the conter after a software LPM delay update
signal s_start : std_logic_vector (1 downto 0);
signal s_stop : std_logic_vector (1 downto 0);
signal s_hold1 : std_logic_vector (1 downto 0);
signal s_hold2 : std_logic_vector (1 downto 0);
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -129,9 +136,32 @@ architecture rtl_linacMON_leds of linacMON_leds is
end process;
-- Error if no SPM signal is detected after n mn.
process (p_reset, p_inTTL(0), s_rstCNT2, p_clk1kHz)
-- Set the status bit
process (p_reset, p_inTTL(0), s_stop(0))
begin
if ((s_stop(0) = '1') or (p_reset = '1')) then
s_start(0) <= '0';
elsif (rising_edge(p_inTTL(0))) then
s_start(0) <= '1';
end if;
end process;
process (p_reset, s_start(0), p_clk1kHz)
begin
if ((s_start(0) = '0') or (p_reset = '1')) then
s_hold1(0) <= '0';
s_hold2(0) <= '0';
s_stop(0) <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1(0) <= '1';
s_hold2(0) <= s_hold1(0);
s_stop(0) <= s_hold2(0);
end if;
end process;
process (p_reset, s_stop(0), s_rstCNT2, p_clk1kHz)
begin
if ((p_inTTL(0) = '1') or (p_reset = '1') or (s_rstCNT2 = '1')) then
if ((s_stop(0) = '1') or (p_reset = '1') or (s_rstCNT2 = '1')) then
s_cnt2 <= (OTHERS => '0');
p_delayError(0) <= '0'; -- red LED OFF
elsif (rising_edge(p_clk1kHz)) then
......@@ -146,9 +176,32 @@ architecture rtl_linacMON_leds of linacMON_leds is
end process;
-- Error if no LPM signal is detected after n mn.
process (p_reset, p_inTTL(1), s_rstCNT3, p_clk1kHz)
-- Set the status bit
process (p_reset, p_inTTL(1), s_stop(1))
begin
if ((s_stop(1) = '1') or (p_reset = '1')) then
s_start(1) <= '0';
elsif (rising_edge(p_inTTL(1))) then
s_start(1) <= '1';
end if;
end process;
process (p_reset, s_start(1), p_clk1kHz)
begin
if ((s_start(1) = '0') or (p_reset = '1')) then
s_hold1(1) <= '0';
s_hold2(1) <= '0';
s_stop(1) <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1(1) <= '1';
s_hold2(1) <= s_hold1(1);
s_stop(1) <= s_hold2(1);
end if;
end process;
process (p_reset, s_stop(1), s_rstCNT3, p_clk1kHz)
begin
if ((p_inTTL(1) = '1') or (p_reset = '1') or (s_rstCNT3 = '1')) then
if ((s_stop(1) = '1') or (p_reset = '1') or (s_rstCNT3 = '1')) then
s_cnt3 <= (OTHERS => '0');
p_delayError(1) <= '0';
elsif (rising_edge(p_clk1kHz)) then
......
fpga/sources/src_linacMON/linacMON_monitoring.vhdl
View file @ 686fe9ce
......@@ -9,7 +9,7 @@
-- File : linacMON_monitoring.vhdl
-- Revision : x.x.x
-- Created : July 10, 2013
-- Updated : July 31, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -34,7 +34,9 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Monitoring now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -72,6 +74,10 @@ architecture rtl_linacMON_monitoring of linacMON_monitoring is
------------------------------------------------------------------------------
signal s_SPMcnt : unsigned (31 downto 0); -- counter
signal s_LPMcnt : unsigned (31 downto 0); -- counter
signal s_start : std_logic_vector (1 downto 0);
signal s_stop : std_logic_vector (1 downto 0);
signal s_hold1 : std_logic_vector (1 downto 0);
signal s_hold2 : std_logic_vector (1 downto 0);
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -79,9 +85,31 @@ architecture rtl_linacMON_monitoring of linacMON_monitoring is
begin
-- SPM monitoring
process (p_reset, p_inTTL(0), p_clk1kHz)
process (p_reset, p_inTTL(0), s_stop(0))
begin
if ((s_stop(0) = '1') or (p_reset = '1')) then
s_start(0) <= '0';
elsif (rising_edge(p_inTTL(0))) then
s_start(0) <= '1';
end if;
end process;
process (p_reset, s_start(0), p_clk1kHz)
begin
if ((s_start(0) = '0') or (p_reset = '1')) then
s_hold1(0) <= '0';
s_hold2(0) <= '0';
s_stop(0) <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1(0) <= '1';
s_hold2(0) <= s_hold1(0);
s_stop(0) <= s_hold2(0);
end if;
end process;
process (p_reset, s_stop(0), p_clk1kHz)
begin
if ((p_inTTL(0) = '1') or (p_reset = '1')) then
if ((s_stop(0) = '1') or (p_reset = '1')) then
s_SPMcnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_SPMcnt < s_SPMcntmax) then
......@@ -93,9 +121,31 @@ architecture rtl_linacMON_monitoring of linacMON_monitoring is
end process;
-- LPM monitoring
process (p_reset, p_inTTL(1), p_clk1kHz)
process (p_reset, p_inTTL(1), s_stop(1))
begin
if ((s_stop(1) = '1') or (p_reset = '1')) then
s_start(1) <= '0';
elsif (rising_edge(p_inTTL(1))) then
s_start(1) <= '1';
end if;
end process;
process (p_reset, s_start(1), p_clk1kHz)
begin
if ((s_start(1) = '0') or (p_reset = '1')) then
s_hold1(1) <= '0';
s_hold2(1) <= '0';
s_stop(1) <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1(1) <= '1';
s_hold2(1) <= s_hold1(1);
s_stop(1) <= s_hold2(1);
end if;
end process;
process (p_reset, s_stop(1), p_clk1kHz)
begin
if ((p_inTTL(1) = '1') or (p_reset = '1')) then
if ((s_stop(1) = '1') or (p_reset = '1')) then
s_LPMcnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_LPMcnt < s_LPMcntmax) then
......
fpga/sources/src_linacMP/linacMP_leds.vhdl
View file @ 686fe9ce
......@@ -17,7 +17,7 @@
-- File : linacMP_leds.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -42,7 +42,9 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication red LED now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -87,6 +89,10 @@ architecture rtl_linacMP_leds of linacMP_leds is
signal s_greenLedON : std_logic;
signal s_blink : std_logic;
signal s_rstCNT : std_logic; -- reset the conter after a software delay update
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -125,9 +131,31 @@ architecture rtl_linacMP_leds of linacMP_leds is
-- Red LED
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after n mn.
process (p_reset, p_inTTL, s_rstCNT, p_clk1kHz)
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, s_rstCNT, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
if ((s_stop = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
s_cnt2 <= (OTHERS => '0');
p_led(0) <= '0'; -- red LED OFF
elsif (rising_edge(p_clk1kHz)) then
......
fpga/sources/src_linacMP/linacMP_monitoring.vhdl
View file @ 686fe9ce
......@@ -9,7 +9,7 @@
-- File : linacMP_monitoring.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -34,7 +34,9 @@
--
--------------------------------------------------------------------------------
-- Modifications :
--
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication monitoring now reacts on rising edge of the signal instead
-- of level
--------------------------------------------------------------------------------
library ieee;
......@@ -67,16 +69,42 @@ architecture rtl_linacMP_monitoring of linacMP_monitoring is
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt : unsigned (31 downto 0); -- counter
signal s_cnt : unsigned (31 downto 0); -- counter
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
process (p_reset, p_inTTL, p_clk1kHz)
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1')) then
if ((s_stop = '1') or (p_reset = '1')) then
s_cnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_cnt < s_cntmax) then
......
fpga/sources/top.vhdl
View file @ 686fe9ce
......@@ -7,7 +7,7 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 27, 2013
-- Updated : November 29, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -43,6 +43,8 @@
-- Version 1.6.0 ; November 18 2013 ; Jean-Paul Ricaud
-- * Multiplexed cPCI registers to overlap them depending on the
-- configuration (duplication, top-up, etc.)
-- * Duplication monitoring now reacts on rising edge of the signal instead
-- of level
--
--------------------------------------------------------------------------------
......@@ -115,8 +117,8 @@ architecture rtl_top of top is
-- signal is received
signal s_topUpGateWidth : std_logic_vector (31 downto 0); -- width of the gating windows
signal s_linacMPMissingPulseDelay : std_logic_vector (31 downto 0); -- maximum delay before a missing
signal s_dupPulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_linacMPPulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_dupPulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_linacMPPulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_linacMONSPMMon : std_logic_vector (31 downto 0);
signal s_linacMONMissingSPMDelay : std_logic_vector (31 downto 0);
signal s_linacMONLPMMon : std_logic_vector (31 downto 0);
......
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