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Beam Positoning Monitor - Gateware
Commit 07e00989 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/wbgen/*: (2/3) add regular delay control register

parent 2b8105dd
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hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
View file @ 07e00989
......@@ -73,6 +73,9 @@ port
adc_data_fe_d1_en_i : in std_logic;
adc_data_fe_d2_en_i : in std_logic;
adc_data_rg_d1_en_i : in std_logic;
adc_data_rg_d2_en_i : in std_logic;
-----------------------------
-- ADC output signals
-----------------------------
......@@ -100,10 +103,11 @@ architecture rtl of fmc516_adc_data is
-- ADC data signals
signal adc_data_ddr_ibufds : std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
signal adc_data_ddr_dly : std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
signal adc_data_fe_sdr : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_sdr : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff_d1 : std_logic_vector(c_num_adc_bits-1 downto 0);
--signal adc_data_ff_d2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ff_d2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_bufg_sync : std_logic_vector(c_num_adc_bits-1 downto 0);
-- Delay signals
......@@ -111,9 +115,13 @@ architecture rtl of fmc516_adc_data is
signal adc_data_fe : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge
signal adc_data_fe_d1 : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed1
signal adc_data_fe_d2 : std_logic_vector(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed2
signal adc_data_rg_d1 : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data delayed1
signal adc_data_rg_d2 : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data delayed2
signal adc_data_d1 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed1
signal adc_data_d2 : t_adc_data_delay_array(c_num_adc_bits/2-1 downto 0); -- ADC data falling edge delayed2
signal adc_data_d3 : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data delayed1
signal adc_data_d4 : std_logic_vector(c_num_adc_bits-1 downto 0); -- ADC data delayed1
-- FIFO signals
signal adc_fifo_full : std_logic;
......@@ -286,12 +294,32 @@ begin
adc_data_d2(i)(1) <= adc_data_fe_d2(i) when adc_data_fe_d2_en_i = '1' else adc_data_d1(i)(1);
adc_data_d2(i)(0) <= adc_data_d1(i)(0);
-- Grorup all the delayed bits.
adc_data_sdr(2*i) <= adc_data_d2(i)(0);
adc_data_sdr(2*i+1) <= adc_data_d2(i)(1);
-- Grorup all the falling edge delayed bits.
adc_data_fe_sdr(2*i) <= adc_data_d2(i)(0);
adc_data_fe_sdr(2*i+1) <= adc_data_d2(i)(1);
end generate;
-- Delay the whole channel by 1 or 2 cycles
p_delay_rg_delay : process(adc_clk_bufr_i)
begin
if rising_edge (adc_clk_bufr_i) then
if sys_rst_n_i = '0' then
adc_data_rg_d1 <= (others => '0');
adc_data_rg_d2 <= (others => '0');
else
adc_data_rg_d1 <= adc_data_fe_sdr;
adc_data_rg_d2 <= adc_data_rg_d1;
end if;
end if;
end process;
-- adc data words delay software-controlled via adc_data_rg_d1_en and adc_data_rg_d2_en
adc_data_d3 <= adc_data_rg_d1 when adc_data_rg_d1_en_i = '1' else adc_data_fe_sdr;
adc_data_d4 <= adc_data_rg_d2 when adc_data_rg_d2_en_i = '1' else adc_data_d3;
adc_data_sdr <= adc_data_d4;
-- Some FF to solve timing problem
p_adc_data_ff : process(adc_clk_bufr_i)
begin
......@@ -299,11 +327,11 @@ begin
if sys_rst_n_i = '0' then
adc_data_ff <= (others => '0');
adc_data_ff_d1 <= (others => '0');
--adc_data_ff_d2 <= (others => '0');
adc_data_ff_d2 <= (others => '0');
else
adc_data_ff <= adc_data_sdr;
adc_data_ff_d1 <= adc_data_ff;
--adc_data_ff_d2 <= adc_data_ff_d1;
adc_data_ff_d2 <= adc_data_ff_d1;
end if;
end if;
end process;
......@@ -320,7 +348,7 @@ begin
--
-- -- write port
-- wr_clk => adc_clk_bufr_i,
-- din => adc_data_ff_d1,
-- din => adc_data_ff_d2,
-- wr_en => adc_fifo_wr,
-- full => adc_fifo_full,
--
......@@ -341,7 +369,7 @@ begin
--
-- -- write port
-- wr_clk => adc_clk_bufr_i,
-- din => adc_data_ff_d1,
-- din => adc_data_ff_d2,
-- wr_en => adc_fifo_wr,
-- full => adc_fifo_full,
--
......@@ -365,7 +393,7 @@ begin
-- write port
clk_wr_i => adc_clk_bufr_i,
d_i => adc_data_ff_d1,
d_i => adc_data_ff_d2,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
......@@ -393,7 +421,7 @@ begin
-- write port
clk_wr_i => adc_clk_bufr_i,
d_i => adc_data_ff_d1,
d_i => adc_data_ff_d2,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
View file @ 07e00989
......@@ -240,6 +240,9 @@ architecture rtl of fmc516_adc_iface is
adc_data_fe_d1_en_i : in std_logic;
adc_data_fe_d2_en_i : in std_logic;
adc_data_rg_d1_en_i : in std_logic;
adc_data_rg_d2_en_i : in std_logic;
-----------------------------
-- ADC output signals.
-----------------------------
......@@ -381,9 +384,14 @@ begin
adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
-- Falling edge delay control
adc_data_fe_d1_en_i => adc_dly_ctl_i(i).adc_data_fe_d1_en,
adc_data_fe_d2_en_i => adc_dly_ctl_i(i).adc_data_fe_d2_en,
-- Regular delay control
adc_data_rg_d1_en_i => adc_dly_ctl_i(i).adc_data_rg_d1_en,
adc_data_rg_d2_en_i => adc_dly_ctl_i(i).adc_data_rg_d2_en,
-----------------------------
-- ADC output signals.
-----------------------------
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
View file @ 07e00989
......@@ -84,8 +84,10 @@ package fmc516_pkg is
type t_adc_dly_reg_array is array (natural range<>) of t_adc_dly_reg;
-- ADC falling edge delay control
-- ADC falling edge and regular delay control (per channel)
type t_adc_dly_ctl is record
adc_data_rg_d1_en : std_logic;
adc_data_rg_d2_en : std_logic;
adc_data_fe_d1_en : std_logic;
adc_data_fe_d2_en : std_logic;
end record;
......
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 07e00989
......@@ -817,6 +817,16 @@ begin
adc_dly_ctl(3).adc_data_fe_d1_en <= regs_out.ch3_dly_ctl_fe_dly_o(0);
adc_dly_ctl(3).adc_data_fe_d2_en <= regs_out.ch3_dly_ctl_fe_dly_o(1);
-- ADC regular delay control
adc_dly_ctl(0).adc_data_rg_d1_en <= regs_out.ch0_dly_ctl_rg_dly_o(0);
adc_dly_ctl(0).adc_data_rg_d2_en <= regs_out.ch0_dly_ctl_rg_dly_o(1);
adc_dly_ctl(1).adc_data_rg_d1_en <= regs_out.ch1_dly_ctl_rg_dly_o(0);
adc_dly_ctl(1).adc_data_rg_d2_en <= regs_out.ch1_dly_ctl_rg_dly_o(1);
adc_dly_ctl(2).adc_data_rg_d1_en <= regs_out.ch2_dly_ctl_rg_dly_o(0);
adc_dly_ctl(2).adc_data_rg_d2_en <= regs_out.ch2_dly_ctl_rg_dly_o(1);
adc_dly_ctl(3).adc_data_rg_d1_en <= regs_out.ch3_dly_ctl_rg_dly_o(0);
adc_dly_ctl(3).adc_data_rg_d2_en <= regs_out.ch3_dly_ctl_rg_dly_o(1);
-- Wishbone Interface Register output assignments. There are others registers
-- not assigned here.
fmc_clk_sel_o <= regs_out.fmc_ctl_clk_sel_o;
......@@ -863,6 +873,8 @@ begin
gen_adc_dly_ctl : for i in 0 to c_num_adc_channels-1 generate
adc_dly_ctl_in(i).adc_data_fe_d1_en <= adc_dly_ctl(i).adc_data_fe_d1_en;
adc_dly_ctl_in(i).adc_data_fe_d2_en <= adc_dly_ctl(i).adc_data_fe_d2_en;
adc_dly_ctl_in(i).adc_data_rg_d1_en <= adc_dly_ctl(i).adc_data_rg_d1_en;
adc_dly_ctl_in(i).adc_data_rg_d2_en <= adc_dly_ctl(i).adc_data_rg_d2_en;
end generate;
-----------------------------
......
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