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Beam Positoning Monitor - Gateware
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Beam Positoning Monitor - Gateware
Commits
2733e2db
Commit
2733e2db
authored
Jan 02, 2013
by
Adrian Byszuk
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Almost working, last fixes for mult-desc case needed
parent
957f0c0c
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6 changed files
with
1293 additions
and
455 deletions
+1293
-455
tx_Mem_Reader.vhd
hdl/modules/pcie/common/tx_Mem_Reader.vhd
+1
-1
tx_Transact.vhd
hdl/modules/pcie/common/tx_Transact.vhd
+3
-3
helper_tasks.v
hdl/sim/pcie/helper_tasks.v
+0
-3
Test01.wcfg
hdl/testbench/pcie/Test01.wcfg
+884
-0
tf64_pcie_axi.v
hdl/testbench/pcie/tf64_pcie_axi.v
+403
-446
bpm_pcie_k7.vhd
hdl/top/pcie/bpm_pcie_k7.vhd
+2
-2
No files found.
hdl/modules/pcie/common/tx_Mem_Reader.vhd
View file @
2733e2db
...
...
@@ -723,7 +723,7 @@ begin
else
eb_FIFO_qout_shift
when
(
eb_FIFO_Hit
=
'1'
and
Shift_1st_QWord_k
=
'1'
)
else
(
others
=>
'0'
);
DDR_Dout_wire
<=
DDR_FIFO_RdQout
when
DDR_FIFO_Hit
=
'1'
else
(
others
=>
'0'
);
Regs_RdQout_wire
<=
Regs_RdQout
(
31
downto
0
)
&
Regs_RdQout
(
63
downto
32
)
--watch out!
Regs_RdQout_wire
<=
Regs_RdQout
--watch out!
when
Regs_Hit
=
'1'
else
(
others
=>
'0'
);
mbuf_Din_wire_OR
<=
eb_FIFO_Dout_wire
or
DDR_Dout_wire
or
Regs_RdQout_wire
;
...
...
hdl/modules/pcie/common/tx_Transact.vhd
View file @
2733e2db
...
...
@@ -386,8 +386,8 @@ begin
-- Always deasserted
s_axis_tx_tdsc_i
<=
'
1
'
;
s_axis_tx_terrfwd_i
<=
'
1
'
;
s_axis_tx_tdsc_i
<=
'
0
'
;
s_axis_tx_terrfwd_i
<=
'
0
'
;
-- s_axis_tx_tkeep_i <= (OTHERS=>'0');
...
...
@@ -1070,7 +1070,7 @@ begin
mbuf_RE_ok
<=
'1'
;
else
-- 3DW header
-- s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+64 downto 64);
s_axis_tx_tdata_i
<=
mbuf_Qout
(
C_DBUS_WIDTH
-1
-32
downto
0
)
s_axis_tx_tdata_i
<=
mbuf_Qout
(
C_DBUS_WIDTH
-1
downto
32
)
&
Trn_Qout_reg
(
C_DBUS_WIDTH
+
32-1
downto
C_DBUS_WIDTH
);
trn_tsof_n_i
<=
'1'
;
s_axis_tx_tlast_i
<=
not
(
mbuf_Qout
(
C_DBUS_WIDTH
));
...
...
hdl/sim/pcie/helper_tasks.v
View file @
2733e2db
...
...
@@ -133,9 +133,6 @@ endtask // Copy_rnd_data
board
.
Hdr_Array
[
2
]
;
hdr_type
=
board
.
Hdr_Array
[
0
]
&
hdr_mask
;
$
display
(
"addr=%x, hdr_type=%x"
,
sys_addr
,
hdr_type
)
;
$
display
(
"hdr=%x, mwr3=%x"
,
board
.
Hdr_Array
[
0
]
,
`HEADER0_MWR3_
)
;
if
((
board
.
Hdr_Array
[
0
]
&
32'hFF000000
)
==
`HEADER0_MWR4_
)
begin
board
.
RP
.
tx_usrapp
.
TSK_TX_MEMORY_WRITE_64
(
board
.
Hdr_Array
[
1
][
15
:
8
]
,
board
.
Hdr_Array
[
0
][
22
:
20
]
,
...
...
hdl/testbench/pcie/Test01.wcfg
View file @
2733e2db
This diff is collapsed.
Click to expand it.
hdl/testbench/pcie/tf64_pcie_axi.v
View file @
2733e2db
This diff is collapsed.
Click to expand it.
hdl/top/pcie/bpm_pcie_k7.vhd
View file @
2733e2db
...
...
@@ -1001,8 +1001,8 @@ architecture Behavioral of bpm_pcie_k7 is
--S SIMONE: Wanxau UserLogic Signals, not Used
signal
protocol_link_act
:
std_logic_vector
(
2-1
downto
0
)
:
=
(
others
=>
'0'
);
signal
protocol_rst
:
std_logic
;
signal
daq_rstop
:
std_logic
;
signal
protocol_rst
:
std_logic
;
signal
daq_rstop
:
std_logic
:
=
'0'
;
signal
ctl_rv
:
std_logic
;
signal
ctl_rd
:
std_logic_vector
(
C_DBUS_WIDTH
/
2-1
downto
0
);
signal
ctl_ttake
:
std_logic
;
...
...
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