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Beam Positoning Monitor - Gateware
Commit 2e83be15 authored by Adrian Byszuk's avatar Adrian Byszuk
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Update simulation models for PCIe RC & DDR memory

parent 8b84e235
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hdl/sim/ddr_model/Manifest.py
View file @ 2e83be15
#don't specify parameters file, because it's only included, not compiled
files = ["wiredly.v"]
if (target == "xilinx" and syn_device[0:4].upper()=="XC6V"): # Virtex6
modules = { "local" : ["virtex6"] }
print("[sim:ddr_model] Using FPGA family: " + syn_device)
elif (target == "xilinx" and syn_device[0:4].upper()=="XC7A"): # Artix7
if (target == "xilinx" and syn_device[0:4].upper()=="XC7A"): # Artix7
modules = { "local" : ["artix7"] }
print("[sim:ddr_model] Using FPGA family: " + syn_device)
#elif (target == "xilinx" and syn_device[0:4].upper()=="XC7K"): # Kintex7
# modules = { "local" : ["kintex7"] }
# print("[sim:ddr_model] Using FPGA family: " + syn_device)
elif (target == "xilinx" and syn_device[0:4].upper()=="XC7K"): # Kintex7
modules = { "local" : ["kintex7"] }
print("[sim:ddr_model] Using FPGA family: " + syn_device)
else:
print("[sim:ddr_model] Unsupported FPGA family: " + syn_device)
hdl/sim/ddr_model/artix7/ddr3_model_parameters.vh
View file @ 2e83be15
......@@ -815,7 +815,7 @@
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 1; // Turn on Debug messages
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
......
hdl/sim/ddr_model/virtex6/Manifest.py → hdl/sim/ddr_model/kintex7/Manifest.py
View file @ 2e83be15
#don't specify parameters file, because it's only included, not compiled
files = ["ddr3_model.v"]
files = ["ddr3_model.sv"]
hdl/sim/ddr_model/wiredly.v
View file @ 2e83be15
......@@ -49,7 +49,7 @@
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.9
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
......
hdl/sim/pcie/board_common.v → hdl/sim/pcie/board_common.vh
View file @ 2e83be15
......@@ -48,8 +48,8 @@
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : board_common.v
// Version : 1.8
// File : board_common.vh
// Version : 3.1
//--
//--------------------------------------------------------------------------------
......@@ -83,5 +83,4 @@
`define PCI_EXP_MEM_WRITE64 7'b1100000
`define PCI_EXP_MSG_DATA 7'b1110xxx
`define TRN_RX_TIMEOUT 5000
`define TRN_RX_TIMEOUT 8000
hdl/sim/pcie/pci_exp_expect_tasks.v → hdl/sim/pcie/pci_exp_expect_tasks.vh
View file @ 2e83be15
......@@ -48,8 +48,8 @@
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_expect_tasks.v
// Version : 1.8
// File : pci_exp_expect_tasks.vh
// Version : 3.1
//--------------------------------------------------------------------------------
`define EXPECT_CPLD_PAYLOAD board.RP.tx_usrapp.expect_cpld_payload
......
hdl/sim/pcie/pci_exp_usrapp_cfg.v
View file @ 2e83be15
......@@ -49,11 +49,11 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_cfg.v
// Version : 1.8
// Version : 3.1
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
`include "board_common.vh"
module pci_exp_usrapp_cfg (
......
hdl/sim/pcie/pci_exp_usrapp_com.v
View file @ 2e83be15
......@@ -49,11 +49,11 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_com.v
// Version : 1.8
// Version : 3.1
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
`include "board_common.vh"
module pci_exp_usrapp_com ();
......@@ -638,6 +638,6 @@ end
end
endtask // TSK_READ_DATA_128
`include "pci_exp_expect_tasks.v"
`include "pci_exp_expect_tasks.vh"
endmodule // pci_exp_usrapp_com
hdl/sim/pcie/pci_exp_usrapp_pl.v
View file @ 2e83be15
......@@ -49,10 +49,10 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_pl.v
// Version : 1.8
// Version : 3.1
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pci_exp_usrapp_pl (
pl_initial_link_width,
......@@ -100,7 +100,7 @@ input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1;
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2;
reg pl_directed_link_auton;
reg [1:0] pl_directed_link_change;
......
hdl/sim/pcie/pci_exp_usrapp_rx.v
View file @ 2e83be15
......@@ -49,11 +49,11 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_rx.v
// Version : 1.8
// Version : 3.1
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
`include "board_common.vh"
`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
module pci_exp_usrapp_rx #(
......@@ -90,7 +90,7 @@ input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
input trn_rerrfwd_n;
input [6 : 0] trn_rbar_hit_n;
input [(7 - 1):0] trn_rbar_hit_n;
input trn_clk;
input trn_reset_n;
......
hdl/sim/pcie/pci_exp_usrapp_tx.v
View file @ 2e83be15
......@@ -49,14 +49,15 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_tx.v
// Version : 1.8
// Version : 3.1
//
//------------------------------------------------------------------------------
`include "board_common.v"
`include "board_common.vh"
module pci_exp_usrapp_tx #(
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2) (
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2
) (
trn_td,
trn_trem_n,
......@@ -304,7 +305,7 @@ end
begin
// $display("[%t] %m: No TESTNAME specified!", $realtime);
// $finish(2);
testname = "sample_smoke_test0";
testname = "pio_writeReadBack_test0";
$display("Running default test {%0s}......", testname);
end
expect_status = 0;
......@@ -328,7 +329,7 @@ end
$display("[%t] %m: Invalid TESTNAME: %0s", $realtime, testname);
$finish(2);
end
`include "tests.v"
`include "tests.vh"
else begin
$display("[%t] %m: Error: Unrecognized TESTNAME: %0s", $realtime, testname);
$finish(2);
......@@ -385,14 +386,14 @@ end
$display("[%t] : Check Max Link Speed = 5.0GT/s - PASSED", $realtime);
end else begin
$display("[%t] : Check Max Link Speed - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "2", P_READ_DATA[19:16]);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read Data %x", $realtime, "1", P_READ_DATA[19:16]);
end
if (P_READ_DATA[23:20] == 4'h04)
$display("[%t] : Check Negotiated Link Width = 04x - PASSED", $realtime);
if (P_READ_DATA[23:20] == 4'h4)
$display("[%t] : Check Negotiated Link Width = 4x - PASSED", $realtime);
else
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "04", P_READ_DATA[23:20]);
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "4", P_READ_DATA[23:20]);
// Check Device/Vendor ID
......@@ -405,6 +406,8 @@ end
error_check = 1;
end else begin
$display("[%t] : Check Device/Vendor ID - PASSED", $realtime);
end
......@@ -1132,7 +1135,7 @@ end
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
REQUESTER_ID,
tag_,
8'b00,
32'b0
......@@ -1210,7 +1213,7 @@ end
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
REQUESTER_ID,
tag_,
1'b0,
lower_addr_,
......@@ -1710,7 +1713,7 @@ end
begin
if (verbose) $display("[%t] : MEMREAD64, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_MEMORY_READ_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0],
TSK_TX_MEMORY_READ_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[bar_index+1][31:0],
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF);
......@@ -2428,7 +2431,7 @@ end
// Read PCIe Device Control Register
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h60, 4'h1);
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h68, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);
......
hdl/sim/pcie/pcie_2_1_rport_7x.v
View file @ 2e83be15
This diff is collapsed.
hdl/sim/pcie/pcie_axi_trn_bridge.v
View file @ 2e83be15
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_axi_trn_bridge.v
// Version : 1.8
// Version : 3.1
//
// Description : AXI - TRN Bridge for Root Port Model.
// Root Port Usrapp's require TRN interface.
......
hdl/sim/pcie/sample_tests1.v → hdl/sim/pcie/sample_tests1.vh
View file @ 2e83be15
......@@ -103,7 +103,7 @@ join
if (test_vars[0] == 1) begin
$display("[%t] : TEST PASSED --- Finished transmission of PCI-Express TLPs", $realtime);
$display("Test Completed Successfully");
$display ("Test Completed Successfully");
end
else begin
$display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
......@@ -235,9 +235,10 @@ begin
begin
$display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
$realtime, {board.RP.tx_usrapp.DATA_STORE[3],board.RP.tx_usrapp.DATA_STORE[2],
board.RP.tx_usrapp.DATA_STORE[1],board.RP.tx_usrapp.DATA_STORE[0]},
board.RP.tx_usrapp.P_READ_DATA);
board.RP.tx_usrapp.DATA_STORE[1],board.RP.tx_usrapp.DATA_STORE[0]},
board.RP.tx_usrapp.P_READ_DATA);
test_failed_flag = 1;
end
else
begin
......@@ -298,7 +299,6 @@ begin
board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
board.RP.tx_usrapp.DATA_STORE[0]}, board.RP.tx_usrapp.P_READ_DATA);
test_failed_flag = 1;
end
else
begin
......@@ -321,6 +321,6 @@ begin
$display("[%t] : Finished transmission of PCI-Express TLPs", $realtime);
if (!test_failed_flag) begin
$display ("Test Completed Successfully");
end
end
$finish;
end
hdl/sim/pcie/sys_clk_gen.v
View file @ 2e83be15
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen.v
// Version : 1.7
// Version : 3.1
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
......
hdl/sim/pcie/sys_clk_gen_ds.v
View file @ 2e83be15
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen_ds.v
// Version : 1.7
// Version : 3.1
//--
//--------------------------------------------------------------------------------
......
hdl/sim/pcie/tests.v deleted 100644 → 0
View file @ 8b84e235
`include "sample_tests1.v"
`include "tf64_pcie_axi.v"
hdl/sim/pcie/tests.vh 0 → 100644
View file @ 2e83be15
`include "sample_tests1.vh"
`include "tf64_pcie_axi.vh"
hdl/sim/pcie/xilinx_pcie_2_1_rport_7x.v
View file @ 2e83be15
......@@ -49,19 +49,19 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_rport_7x.v
// Version : 1.8
// Version : 3.1
//
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
`include "board_common.v"
`include "board_common.vh"
module xilinx_pcie_2_1_rport_7x # (
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking Module //postsynthsim changes
parameter PL_FAST_TRAIN = "FALSE",
parameter ALLOW_X8_GEN2 = "FALSE",
parameter C_DATA_WIDTH = 64,
......@@ -69,7 +69,7 @@ module xilinx_pcie_2_1_rport_7x # (
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter DEVICE_ID = 16'h506F,
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h1,
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
parameter USER_CLK_FREQ = 3,
......@@ -192,67 +192,22 @@ module xilinx_pcie_2_1_rport_7x # (
wire [21:0] m_axis_rx_tuser;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire PIPE_RXUSRCLK_IN;
wire [3:0] PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [3:0] PIPE_RXOUTCLK_OUT;
wire [3:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
wire PIPE_OOBCLK_IN;
wire pipe_pclk_in;
wire pipe_rxusrclk_in;
wire [3:0] pipe_rxoutclk_in;
wire pipe_dclk_in;
wire pipe_userclk1_in;
wire pipe_userclk2_in;
wire pipe_mmcm_lock_in;
wire pipe_txoutclk_out;
wire [3:0] pipe_rxoutclk_out;
wire [3:0] pipe_pclk_sel_out;
wire pipe_gen3_out;
wire pipe_oobclk_in;
assign trn_reset_n = !user_reset_out;
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
localparam USER_CLK_FREQ = USER_CLK_FREQ;
localparam USER_CLK2_DIV2 = USER_CLK2_DIV2;
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
//---------- PIPE Clock Module -------------------------------------------------
pcie_core_pipe_clock #
(
.PCIE_ASYNC_EN ("FALSE"), // PCIe async enable
.PCIE_TXBUF_EN ("FALSE"), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (6'h04), // PCIe number of lanes
.PCIE_LINK_SPEED ( 2 ),
.PCIE_REFCLK_FREQ (0), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (USER_CLK_FREQ +1), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (USERCLK2_FREQ +1), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk) ,
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_OOBCLK ( PIPE_OOBCLK_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
// PCI-Express FPGA Endpoint Instance
pcie_2_1_rport_7x # (
......@@ -290,19 +245,19 @@ module xilinx_pcie_2_1_rport_7x # (
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface - For Partial Reconfig Support //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
.pipe_pclk_in ( pipe_pclk_in ),
.pipe_rxusrclk_in ( pipe_rxusrclk_in ),
.pipe_rxoutclk_in ( pipe_rxoutclk_in ),
.pipe_dclk_in ( pipe_dclk_in ),
.pipe_userclk1_in ( pipe_userclk1_in ),
.pipe_userclk2_in ( pipe_userclk2_in ),
.pipe_oobclk_in ( pipe_oobclk_in ),
.pipe_mmcm_lock_in ( pipe_mmcm_lock_in ),
.pipe_txoutclk_out ( pipe_txoutclk_out ),
.pipe_rxoutclk_out ( pipe_rxoutclk_out ),
.pipe_pclk_sel_out ( pipe_pclk_sel_out ),
.pipe_gen3_out ( pipe_gen3_out ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
......@@ -333,8 +288,8 @@ module xilinx_pcie_2_1_rport_7x # (
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( ~trn_rnp_ok_n ),
.rx_np_req ( 1'b0 ),
.rx_np_ok ( 1'b1 ),
.rx_np_req ( 1'b1 ),
.fc_cpld ( ),
.fc_cplh ( ),
......@@ -506,6 +461,30 @@ module xilinx_pcie_2_1_rport_7x # (
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.common_commands_in ( 4'b0 ),
.pipe_rx_0_sigs ( 25'b0 ),
.pipe_rx_1_sigs ( 25'b0 ),
.pipe_rx_2_sigs ( 25'b0 ),
.pipe_rx_3_sigs ( 25'b0 ),
.pipe_rx_4_sigs ( 25'b0 ),
.pipe_rx_5_sigs ( 25'b0 ),
.pipe_rx_6_sigs ( 25'b0 ),
.pipe_rx_7_sigs ( 25'b0 ),
.common_commands_out ( ),
.pipe_tx_0_sigs ( ),
.pipe_tx_1_sigs ( ),
.pipe_tx_2_sigs ( ),
.pipe_tx_3_sigs ( ),
.pipe_tx_4_sigs ( ),
.pipe_tx_5_sigs ( ),
.pipe_tx_6_sigs ( ),
.pipe_tx_7_sigs ( ),
.pipe_mmcm_rst_n ( 1'b1 ), // Async | Async
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n )
......
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