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Commit 352cb372 authored by Adrian Byszuk's avatar Adrian Byszuk
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Update PCIe/DDR tesbench 

- HDLMake support is disabled
- only Questa/Modelsim is supported
- should be easy to add XSIM support
parent 2e83be15
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hdl/testbench/pcie/.gitignore
View file @ 352cb372
......@@ -6,7 +6,8 @@ xilinxsim.ini
*.wdb
#ignore temporary simulation files
*.dat
work*
work/*
msim/
fuse*
glbl.v
#modelsim stuff
......@@ -14,4 +15,5 @@ transcript
modelsim.in*
*.wlf
*.version
*.dbg
hdl/testbench/pcie/HDLMAKE_NOT_SUPPORTED 0 → 100644
View file @ 352cb372
As of version 2.1, it's impossible to use HDLMake for simulation.
- HDLMake doesn't support VHDL libraries other than "work"
- it's impossible to pass defines/change compile options per file
- dependency resolution is still flaky
- user has no control over optimisation step. By directly invoking
optimisation with proper parameters I was able cut down simulation time from 1 hour to < 6 minutes
...and I'm still not finished
- few more things that I forgot right now
Therefore only traditionally scripted Questa simulation is now present. Works like a charm.
It shouldn't be difficult to rework these scripts for XSim support. Or directly invoke simulation from Vivado...
hdl/testbench/pcie/Makefile deleted 100644 → 0
View file @ 2e83be15
This diff is collapsed.
hdl/testbench/pcie/Manifest.py
View file @ 352cb372
import os as __os
import shutil as __shutil
def __import_verilog_lib():
xilinx_dir = __os.getenv("XILINX");
if xilinx_dir == None:
print("XILINX variable not set")
__os.exit(-1)
if __os.path.isdir("work"):
return
verilog_lib = xilinx_dir + "/ISE/verilog/src/glbl.v"
print("Copying " + verilog_lib)
#__os.mkdir("work")
__shutil.copy(verilog_lib, ".")
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "board"
#pickup correct top file
#syn_device = "xc7k325t"
syn_device = "xc7a200t"
syn_device = "xc7k325t"
#syn_device = "xc7a200t"
vlog_opt = "+incdir+../../sim/pcie +define+SIMULATION"
# ENABLE_GT has to be set until I figure out a way
# to force ISIM to work in PIPE simulation mode
#vlog_opt += " +define+ENABLE_GT"
vlog_opt = "+incdir+../../sim/pcie +define+SIMULATION +define+ENABLE_GT"
# DDR model options
vlog_opt += " +incdir+../../sim/ddr_model +define+x1Gb +define+sg125 +define+x8"
vlog_opt += " -incr $(XILINX_VIVADO)/data/verilog/src/glbl.v"
vsim_opt = "+TESTNAME=tf64_pcie_axi -t fs -novopt +notimingchecks -L unisims_ver -L secureip -L unimacro_ver glbl"
__import_verilog_lib()
files = ["board.v",
"glbl.v"]
files = ["board.v"]
#top_module = "tf64_pcie_axi"
modules = {"local" : ["../../modules/pcie",
"../../ip_cores/pcie/7a200ffg1156",
"../../ip_cores/pcie/7k325ffg900",
"../../sim/pcie",
"../../sim/ddr_model",
"../../top/pcie"]}
......
hdl/testbench/pcie/Test01.wcfg deleted 100644 → 0
View file @ 2e83be15
This diff is collapsed.
hdl/testbench/pcie/board.f deleted 100644 → 0
View file @ 2e83be15
../../ip_cores/pcie/7k325ffg900/bram_x64.vhd
../../ip_cores/pcie/7k325ffg900/eb_fifo_counted_resized.vhd
../../ip_cores/pcie/7k325ffg900/mbuf_128x72.vhd
../../ip_cores/pcie/7k325ffg900/prime_FIFO_plain.vhd
../../ip_cores/pcie/7k325ffg900/sfifo_15x128.vhd
../../modules/pcie/common/v6abb64Package_efifo_elink.vhd
../../modules/pcie/common/DDR_Blinker.vhd
../../modules/pcie/common/DMA_Calculate.vhd
../../modules/pcie/common/DMA_FSM.vhd
../../modules/pcie/common/FF_tagram64x36.vhd
../../modules/pcie/common/FIFO_Wrapper.vhd
../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd
../../modules/pcie/common/Interrupts.vhd
../../modules/pcie/common/PCIe_UserLogic_00.vhd
../../modules/pcie/common/Registers.vhd
../../modules/pcie/common/RxIn_Delays.vhd
../../modules/pcie/common/Tx_Output_Arbitor.vhd
../../modules/pcie/common/bram_DDRs_Control.vhd
../../modules/pcie/common/bram_DDRs_Control_Loopback.vhd
../../modules/pcie/common/rx_CplD_Channel.vhd
../../modules/pcie/common/rx_MRd_Channel.vhd
../../modules/pcie/common/rx_MWr_Channel.vhd
../../modules/pcie/common/rx_Transact.vhd
../../modules/pcie/common/rx_dsDMA_Channel.vhd
../../modules/pcie/common/rx_usDMA_Channel.vhd
../../modules/pcie/common/tlpControl.vhd
../../modules/pcie/common/tx_Mem_Reader.vhd
../../modules/pcie/common/tx_Transact.vhd
../../top/pcie/bpm_pcie_k7.vhd
hdl/testbench/pcie/board.v
View file @ 352cb372
......@@ -86,11 +86,11 @@ parameter DATA_BUF_ADDR_WIDTH = 5;
parameter DQ_CNT_WIDTH = 6;
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8;
parameter DM_WIDTH = 4;
parameter DM_WIDTH = 8;
// # of DM (data mask)
parameter DQ_WIDTH = 32;
parameter DQ_WIDTH = 64;
// # of DQ (data)
parameter DQS_WIDTH = 4;
parameter DQS_WIDTH = 8;
parameter DQS_CNT_WIDTH = 3;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
......@@ -101,14 +101,14 @@ parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 16;
parameter ROW_WIDTH = 14;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 28;
parameter ADDR_WIDTH = 30;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 0;
parameter USE_CS_PORT = 1;
// # = 1, When CS output is enabled
// = 0, When CS output is disabled
// If CS_N disabled, user must connect
......@@ -183,7 +183,7 @@ parameter CA_MIRROR = "OFF";
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 8000;
parameter CLKIN_PERIOD = 5000;
// Input Clock Period
parameter CLKFBOUT_MULT = 8;
// write PLL VCO multiplier
......@@ -535,20 +535,8 @@ reg DMA_us_is_Last;
//
// PCI-Express Endpoint Instance
//
`ifdef ENABLE_GT
parameter PIPE_SIM = "FALSE";
parameter PIPE_SIM_MODE = "FALSE";
defparam board.RP.rport.PIPE_SIM_MODE = "FALSE";
`else
parameter PIPE_SIM = "TRUE";
parameter PIPE_SIM_MODE = "TRUE";
defparam board.RP.rport.PIPE_SIM_MODE = "TRUE";
`endif
top # (
.PL_FAST_TRAIN("TRUE"),
.PIPE_SIM_MODE(PIPE_SIM_MODE),
.pcieLanes(4),
.SIMULATION("TRUE")
)
EP (
......@@ -794,7 +782,7 @@ endgenerate
//
// Randoms generated for process flow
always @(posedge board.EP.bpm_pcie.user_clk) begin
always @(posedge board.EP.bpm_pcie_i.user_clk) begin
Op_Random[ 31:00] = $random();
Op_Random[ 63:32] = $random();
Op_Random[ 95:64] = $random();
......@@ -812,7 +800,6 @@ initial begin
end
end
`include "pipe_interconnect.v"
initial begin
$display("[%t] : System Reset Asserted...", $realtime);
......
hdl/testbench/pcie/board_vlog.f deleted 100644 → 0
View file @ 2e83be15
board.v
../../sim/pcie/sys_clk_gen.v
../../sim/pcie/sys_clk_gen_ds.v
../../sim/pcie/xilinx_pcie_2_1_rport_7x.v
../../sim/pcie/pcie_2_1_rport_7x.v
../../sim/pcie/pcie_axi_trn_bridge.v
../../sim/pcie/pci_exp_usrapp_com.v
../../sim/pcie/pci_exp_usrapp_tx.v
../../sim/pcie/pci_exp_usrapp_cfg.v
../../sim/pcie/pci_exp_usrapp_rx.v
../../sim/pcie/pci_exp_usrapp_pl.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_drp.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_user.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top_pipe_mode.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_lane.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_thrtl_ctl.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core.v
hdl/testbench/pcie/compile.sh 0 → 100755
View file @ 352cb372
#!/bin/bash -f
bin_path="/opt/Questa/questasim/bin"
ExecStep()
{
"$@"
RETVAL=$?
if [ $RETVAL -ne 0 ]
then
exit $RETVAL
fi
}
ExecStep source ./questa_compile.sh 2>&1 | tee -a compile.log
hdl/testbench/pcie/helper_tasks.v 0 → 100644
View file @ 352cb372
//////////////////
// tf64_pcie_exi defines
/////////////////
//`define RANDOM_SEQUENCE
/* Time parameters */
`define T_DELAY_AFTER 0.0
`define T_DELTA 0.1
`define T_PIO_INTERVAL 50.0
`define T_DMA_INTERVAL 300.0
`define T_RX_NO_FC_PERIOD 1900000.0
`define T_TX_NO_FC_PERIOD 1500000.0
/* Memory size for simulation */
`define C_ARRAY_DIMENSION 4096
/* Start indices */
`define PIO_START_INDEX 'H0300
`define DMA_START_INDEX 'H0000
/* Request completion boundary */
`define C_RCB_16_DW 'H10
`define C_RCB_32_DW 'H20
/* BAR */
`define C_BAR0_HIT 7'H01
`define C_BAR1_HIT 7'H02
`define C_BAR2_HIT 7'H03
`define C_BAR3_HIT 7'H04
`define C_BAR4_HIT 7'H05
`define C_BAR5_HIT 7'H06
`define C_BAR6_HIT 7'H07
`define C_NO_BAR_HIT 7'H00
/* Requester ID and Completer ID */
`define C_HOST_WRREQ_ID 16'H0ABC
`define C_HOST_RDREQ_ID 16'HE1E2
`define C_HOST_CPLD_ID 16'HC01D
/* 1st header */
`define HEADER0_MWR3_ 32'H40000000
`define HEADER0_MWR4_ 32'H60000000
`define HEADER0_MRD3_ 32'H00000000
`define HEADER0_MRD4_ 32'H20000000
`define HEADER0_CPLD 32'H4A000000
`define HEADER0_CPL 32'H0A000000
`define HEADER0_MSG 32'H34000001
/* Message codes */
`define C_MSG_CODE_INTA 8'H20
`define C_MSG_CODE_INTA_N 8'H24
/* Payload type */
`define USE_PRIVATE 1
`define USE_PUBLIC 0
/* General registers */
`define C_ADDR_VERSION 32'H0000
`define C_ADDR_IRQ_STAT 32'H0008
`define C_ADDR_IRQ_EN 32'H0010
`define C_ADDR_SDRAM_PG 32'H001C
`define C_ADDR_GSR 32'H0020
`define C_ADDR_WB_PG 32'H0024
`define C_ADDR_GCR 32'H0028
/* Control registers for special ports */
`define C_ADDR_MRD_CTRL 32'H0074
`define C_ADDR_TX_CTRL 32'H0078
`define C_ADDR_ICAP 32'H007C
`define C_ADDR_EB_STACON 32'H0090
/* Downstream DMA channel registers */
`define C_ADDR_DMA_DS_PAH 32'H0050
`define C_ADDR_DMA_DS_CTRL 32'H006C
`define C_ADDR_DMA_DS_STA 32'H0070
/* Upstream DMA channel registers */
`define C_ADDR_DMA_US_PAH 32'H002C
`define C_ADDR_DMA_US_CTRL 32'H0048
`define C_ADDR_DMA_US_STA 32'H004C
/* DMA-specific constants */
`define C_DMA_RST_CMD 32'H0200000A
// ***************************************** //
// Tasks //
// ***************************************** //
task dword_pack_data_store;
input [31:0] dword;
input [10:0] offset;
begin
board.RP.tx_usrapp.DATA_STORE[offset*4 + 3] = dword[31:24];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 2] = dword[23:16];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 1] = dword[15:8];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 0] = dword[7:0];
end
endtask //dword_pack_data_store
///////////////////////////////////////////////
// Copy random data to tx send buffer //
///////////////////////////////////////////////
task Copy_rnd_data;
reg [7:0] i;
begin
for (i = 0; i <= 100; i = i + 1) begin
board.RP.tx_usrapp.DATA_STORE[i*4 + 3] = board.D_Array[i][31:24];
board.RP.tx_usrapp.DATA_STORE[i*4 + 2] = board.D_Array[i][23:16];
board.RP.tx_usrapp.DATA_STORE[i*4 + 1] = board.D_Array[i][15:8];
board.RP.tx_usrapp.DATA_STORE[i*4 + 0] = board.D_Array[i][7:0];
end
end
endtask // Copy_rnd_data
///////////////////////////////////////////////
// //
// Feed TLP to Rx: MRd, MWr, Cpl/D, Msg //
// //
///////////////////////////////////////////////
task TLP_Feed_Rx;
input [ 6:0] BAR_Hit_N; // Which BAR is hit
reg [63:0] sys_addr;
reg [31:0] hdr_type;
reg [31:0] hdr_mask;
begin
hdr_mask = 32'hFF000000;
hdr_type = board.Hdr_Array[0] & hdr_mask;
if (board.Hdr_Array[0][29]) begin //64bit address
sys_addr[63:32] = board.RP.tx_usrapp.BAR_INIT_P_BAR[BAR_Hit_N] +
board.Hdr_Array[2];
sys_addr[31:0] = board.RP.tx_usrapp.BAR_INIT_P_BAR[BAR_Hit_N - 1];
sys_addr = sys_addr + board.Hdr_Array[3];
end else begin
sys_addr = board.RP.tx_usrapp.BAR_INIT_P_BAR[BAR_Hit_N - 1] +
board.Hdr_Array[2];
end
if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MWR4_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_64(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr,
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MWR3_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr[31:0],
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MRD4_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_64(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr,
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MRD3_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr[31:0],
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_CPLD) begin
board.RP.tx_usrapp.TSK_TX_COMPLETION_DATA(board.Hdr_Array[2][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
board.Hdr_Array[1][11:0],
board.Hdr_Array[2][6:0],
board.Hdr_Array[1][15:13],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_CPL) begin
board.RP.tx_usrapp.TSK_TX_COMPLETION(board.Hdr_Array[2][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
board.Hdr_Array[1][15:13]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MSG) begin
board.RP.tx_usrapp.TSK_TX_MESSAGE(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
0, //board.RP.tx_usrapp.DATA_STORE[7:0],
board.Hdr_Array[0][26:24],
board.Hdr_Array[1][7:0]);
end
else begin
$display("%d ns: TLP_Feed_Rx: unknown header type!", $time);
#10 $finish;
end
end
endtask
/////////////////////////////////////////////
// //
// Function - Endian Inversion 64-bit //
// //
/////////////////////////////////////////////
function [31:00] Inv_Endian;
input [31:00] Data;
begin
Inv_Endian = {Data[ 7: 0], Data[15: 8], Data[23:16], Data[31:24]};
end
endfunction
hdl/testbench/pcie/isim_cmd.tcl deleted 100644 → 0
View file @ 2e83be15
# ISIM Commands
run all
quit
hdl/testbench/pcie/optimise.sh 0 → 100755
View file @ 352cb372
#!/bin/bash -f
bin_path="/opt/Questa/questasim/bin"
ExecStep()
{
"$@"
RETVAL=$?
if [ $RETVAL -ne 0 ]
then
exit $RETVAL
fi
}
ExecStep source ./questa_optimise.sh 2>&1 | tee -a optimise.log
hdl/testbench/pcie/pipe_interconnect.v deleted 100644 → 0
View file @ 2e83be15
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pipe_interconnect.v
// Version : 1.7
`define EP board.EP.bpm_pcie.pcie_core_i.pcie_top_i
`define RP board.RP.rport.pcie_top_i
//---------------------------------------------------------- PIO RTL & RP simulation -------------------------------------------------------------------//
generate
if (PIPE_SIM == "TRUE")
begin
assign `EP.pipe_rx0_char_is_k_gt = `RP.pipe_tx0_char_is_k_gt;
assign `EP.pipe_rx1_char_is_k_gt = `RP.pipe_tx1_char_is_k_gt;
assign `EP.pipe_rx2_char_is_k_gt = `RP.pipe_tx2_char_is_k_gt;
assign `EP.pipe_rx3_char_is_k_gt = `RP.pipe_tx3_char_is_k_gt;
assign `EP.pipe_rx4_char_is_k_gt = `RP.pipe_tx4_char_is_k_gt;
assign `EP.pipe_rx5_char_is_k_gt = `RP.pipe_tx5_char_is_k_gt;
assign `EP.pipe_rx6_char_is_k_gt = `RP.pipe_tx6_char_is_k_gt;
assign `EP.pipe_rx7_char_is_k_gt = `RP.pipe_tx7_char_is_k_gt;
assign `EP.pipe_rx0_data_gt = `RP.pipe_tx0_data_gt;
assign `EP.pipe_rx1_data_gt = `RP.pipe_tx1_data_gt;
assign `EP.pipe_rx2_data_gt = `RP.pipe_tx2_data_gt;
assign `EP.pipe_rx3_data_gt = `RP.pipe_tx3_data_gt;
assign `EP.pipe_rx4_data_gt = `RP.pipe_tx4_data_gt;
assign `EP.pipe_rx5_data_gt = `RP.pipe_tx5_data_gt;
assign `EP.pipe_rx6_data_gt = `RP.pipe_tx6_data_gt;
assign `EP.pipe_rx7_data_gt = `RP.pipe_tx7_data_gt;
//-------------------------------------------------------------------------------------------------------------------------//
assign `RP.pipe_rx0_char_is_k_gt = `EP.pipe_tx0_char_is_k_gt;
assign `RP.pipe_rx1_char_is_k_gt = `EP.pipe_tx1_char_is_k_gt;
assign `RP.pipe_rx2_char_is_k_gt = `EP.pipe_tx2_char_is_k_gt;
assign `RP.pipe_rx3_char_is_k_gt = `EP.pipe_tx3_char_is_k_gt;
assign `RP.pipe_rx4_char_is_k_gt = `EP.pipe_tx4_char_is_k_gt;
assign `RP.pipe_rx5_char_is_k_gt = `EP.pipe_tx5_char_is_k_gt;
assign `RP.pipe_rx6_char_is_k_gt = `EP.pipe_tx6_char_is_k_gt;
assign `RP.pipe_rx7_char_is_k_gt = `EP.pipe_tx7_char_is_k_gt;
assign `RP.pipe_rx0_data_gt = `EP.pipe_tx0_data_gt;
assign `RP.pipe_rx1_data_gt = `EP.pipe_tx1_data_gt;
assign `RP.pipe_rx2_data_gt = `EP.pipe_tx2_data_gt;
assign `RP.pipe_rx3_data_gt = `EP.pipe_tx3_data_gt;
assign `RP.pipe_rx4_data_gt = `EP.pipe_tx4_data_gt;
assign `RP.pipe_rx5_data_gt = `EP.pipe_tx5_data_gt;
assign `RP.pipe_rx6_data_gt = `EP.pipe_tx6_data_gt;
assign `RP.pipe_rx7_data_gt = `EP.pipe_tx7_data_gt;
end
endgenerate
//----------------------------------------------------------------------------------------------------------------------------------------------------------//
hdl/testbench/pcie/questa_compile.sh 0 → 100644
View file @ 352cb372
This diff is collapsed.
hdl/testbench/pcie/questa_optimise.sh 0 → 100644
View file @ 352cb372
######################################################################
#
# Auto generated by Vivado for 'behavioral' simulation
# Modified by Adrian Byszuk
# Uses UNIFAST_VER library to speed up simulation!
#
######################################################################
vopt -64 +acc +notimingchecks -L unifast_ver -L unisims_ver -L unimacro_ver -L secureip -L xil_defaultlib -L fifo_generator_v12_0 \
-L axi_interconnect_v1_7 -L lib_pkg_v1_0 -L lib_fifo_v1_0 -L lib_srl_fifo_v1_0 -L lib_cdc_v1_0 -L axi_datamover_v5_1 \
-work xil_defaultlib xil_defaultlib.board xil_defaultlib.glbl -o board_opt
hdl/testbench/pcie/questa_simulate.do 0 → 100644
View file @ 352cb372
######################################################################
#
# File name : board_simulate.do
# Created on: Thu Sep 24 20:15:17 CEST 2015
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################################################################
vsim +TESTNAME=tf64_pcie_axi -t 1ps +notimingchecks -lib xil_defaultlib board_opt
view wave
view structure
view signals
log -r /board/EP/bpm_pcie_i/theTlpControl/*
log /board/EP/bpm_pcie_i/DDRs_ctrl_module/*
log /board/EP/bpm_pcie_i/*
log /board/*
radix hex
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
#add signals to wave window
do wave.do
run -all
hdl/testbench/pcie/simulate.sh 0 → 100755
View file @ 352cb372
#!/bin/sh -f
bin_path="/opt/Questa/questasim/bin"
ExecStep()
{
"$@"
RETVAL=$?
if [ $RETVAL -ne 0 ]
then
exit $RETVAL
fi
}
ExecStep $bin_path/vsim -64 -do "do {questa_simulate.do}" -l simulate.log
hdl/testbench/pcie/simulate_isim.sh deleted 100755 → 0
View file @ 2e83be15
#!/bin/sh
#TEST=sample_smoke_test0
TEST=tf64_pcie_axi
# compile all of the files
# Include -d ENABLE_GT to run the simulations in GT mode
vlogcomp -work work -d ENABLE_GT -d SIMULATION -i . -i ../../sim/pcie --incremental -f board_vlog.f && \
vhpcomp -work work --incremental -f board.f && \
vlogcomp -work work $XILINX/verilog/src/glbl.v && \
# compile and link source files
fuse work.board work.glbl -d ENABLE_GT -d SIMULATION -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -o tb_sim
# set BATCH_MODE=0 to run simulation in GUI mode
BATCH_MODE=0
if [ $BATCH_MODE == 1 ]; then
# run the simulation in batch mode
./tb_sim -wdb wave_isim -tclbatch isim_cmd.tcl -testplusarg TESTNAME=$TEST
else
# run the simulation in gui mode
./tb_sim -gui -view Test01.wcfg -wdb wave_isim -tclbatch isim_cmd.tcl -testplusarg TESTNAME=$TEST
fi
hdl/testbench/pcie/tf64_pcie_axi.v → hdl/testbench/pcie/tf64_pcie_axi.vh
View file @ 352cb372
......@@ -46,6 +46,9 @@ begin
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
board.RP.tx_usrapp.REQUESTER_ID = 'H01a0; //fix endpoint ID
board.RP.tx_usrapp.COMPLETER_ID_CFG = `C_HOST_CPLD_ID; //fix Root Port ID
$display("\n%d ns: #### Starting test... ####\n", $time);
// Initialization: TLP
# 400
......@@ -124,7 +127,7 @@ begin
board.Rx_MWr_Tag = board.Rx_MWr_Tag + 1;
$display("\n Wait for DDR memory core to finish calibration...");
wait (board.EP.bpm_pcie.ddr_calib_done == 1);
wait (board.EP.bpm_pcie_i.DDRs_ctrl_module.ddr_ready == 1);
/////////////////////////////////////////////////////////////////////
// PIO simulation //
......@@ -185,6 +188,12 @@ begin
board.Rx_MRd_Tag = board.Rx_MRd_Tag + 1;
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != {DATA_STORE[3], DATA_STORE[2], DATA_STORE[1], DATA_STORE[0]}) begin
$display("[%t] Data Mismatch Error: 1st word of received data didn't match sent pattern", $realtime);
$display("\t Sent: %x, Received: %x", {DATA_STORE[3], DATA_STORE[2], DATA_STORE[1], DATA_STORE[0]}, P_READ_DATA);
$finish;
end
// ///////////////////////////////////////////////////////////////////
// PIO write & read BAR[4]
// NOTE: FIFO address is 64-bit aligned, only the lower 32-bit is
......@@ -213,6 +222,11 @@ begin
board.Rx_MRd_Tag = board.Rx_MRd_Tag + 1;
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != {DATA_STORE[3], DATA_STORE[2], DATA_STORE[1], DATA_STORE[0]}) begin
$display("[%d ns:] Data Mismatch Error: 1st word of received data didn't match sent pattern", $time);
$display("\t Sent: %x, Received: %x", {DATA_STORE[3], DATA_STORE[2], DATA_STORE[1], DATA_STORE[0]}, P_READ_DATA);
$finish;
end
$display("%d ns: ### End PIO simulation\n", $time);
......@@ -262,6 +276,7 @@ begin
board.Rx_MRd_Tag = board.Rx_MRd_Tag + 1;
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
board.Rx_TLP_Length = 'H01;
$display("%d ns: Switch DDR page", $time);
board.Hdr_Array[0] = `HEADER0_MWR4_ | board.Rx_TLP_Length[9:0];
......
hdl/testbench/pcie/wave.do
View file @ 352cb372
This diff is collapsed.
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